S. Biesemans

4.5k total citations
171 papers, 2.5k citations indexed

About

S. Biesemans is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Biomedical Engineering. According to data from OpenAlex, S. Biesemans has authored 171 papers receiving a total of 2.5k indexed citations (citations by other indexed papers that have themselves been cited), including 167 papers in Electrical and Electronic Engineering, 40 papers in Atomic and Molecular Physics, and Optics and 9 papers in Biomedical Engineering. Recurrent topics in S. Biesemans's work include Semiconductor materials and devices (152 papers), Advancements in Semiconductor Devices and Circuit Design (124 papers) and Integrated Circuits and Semiconductor Failure Analysis (52 papers). S. Biesemans is often cited by papers focused on Semiconductor materials and devices (152 papers), Advancements in Semiconductor Devices and Circuit Design (124 papers) and Integrated Circuits and Semiconductor Failure Analysis (52 papers). S. Biesemans collaborates with scholars based in Belgium, United States and Netherlands. S. Biesemans's co-authors include Nadine Collaert, M. Jurczak, K. De Meyer, Sven Rogge, G. P. Lansbergen, J. Caro, Thomas Hoffmann, P. Absil, A. Veloso and R. Rooyackers and has published in prestigious journals such as Physical Review Letters, Applied Physics Letters and Journal of Applied Physics.

In The Last Decade

S. Biesemans

164 papers receiving 2.4k citations

Peers

Countries citing papers authored by S. Biesemans

Since Specialization

Citations

This map shows the geographic impact of S. Biesemans's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Biesemans with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Biesemans more than expected).

Fields of papers citing papers by S. Biesemans

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Biesemans. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Biesemans. The network helps show where S. Biesemans may publish in the future.

Co-authorship network of co-authors of S. Biesemans

This figure shows the co-authorship network connecting the top 25 collaborators of S. Biesemans. A scholar is included among the top collaborators of S. Biesemans based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Biesemans. S. Biesemans is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Lithography strategies on overlay control of backside processing in complementary field effect transistor (CFET) device 2025 ·(unknown), (unknown), (unknown), Teresa Rodrigues, Koen D’havé, A. Vandooren, (unknown), (unknown), (unknown), S. Demuynck, Naoto Horiguchi, S. Biesemans, (unknown), Mircea Dusa, Sandip Halder	0
2	Source/Drain Epitaxy for Nanosheet-Based CFET Devices 2024 ·ECS Transactions ·Erik Rosseel, Clément Porret, (unknown), Roger Loo, Hans Mertens, (unknown), (unknown), (unknown), Olivier Richard, J. Geypen, (unknown), (unknown), (unknown), S. Demuynck, Lucas Petersen Barbosa Lima, R. Langer, S. Biesemans, Naoto Horiguchi	2
3	Source/Drain Epitaxy for Nanosheet-Based CFET Devices 2024 ·ECS Meeting Abstracts ·Erik Rosseel, Clément Porret, (unknown), Roger Loo, Hans Mertens, (unknown), (unknown), (unknown), Olivier Richard, J. Geypen, (unknown), (unknown), (unknown), S. Demuynck, Lucas Petersen Barbosa Lima, R. Langer, S. Biesemans, Naoto Horiguchi	0
4	EUV pupil optimization for 32nm pitch logic structures 2018 ·David del Rio, (unknown), Joern-Holger Franke, Mircea Dusa, (unknown), S. Biesemans, Kathleen Nafus, Werner Gillijns, Eric Hendrickx, (unknown), (unknown), (unknown)	2
5	Simulation of Semiconductor Processes and Devices 1998: SISPAD 98 2012 ·Medical Entomology and Zoology ·K. De Meyer, S. Biesemans, (unknown)	4
6	Variability and technology aware SRAM Product yield maximization 2011 ·Symposium on VLSI Technology ·(unknown), (unknown), M. Garcia Bardon, Stefan Cosemans, Philippe Roussel, Petr Dobrovolný, T. Chiarella, Naoto Horiguchi, A. Mercha, T. Y. Hoffmann, Diederik Verkest, S. Biesemans	8
7	Lifetime-Enhanced Transport in Silicon due to Spin and Valley Blockade 2011 ·Physical Review Letters ·G. P. Lansbergen, Rajib Rahman, J. Verduijn, G. C. Tettamanzi, Nadine Collaert, S. Biesemans, Gerhard Klimeck, Lloyd C. L. Hollenberg, Sven Rogge	23
8	Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession 2010 ·Solid-State Electronics ·T. Chiarella, Liesbeth Witters, A. Mercha, C. Kerner, Michał Rakowski, C. Ortolland, (unknown), Bertrand Parvais, A. De Keersgieter, Stefan Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, Thomas Hoffmann	99
9	Temperature dependent electrical characteristics of through-si-via (TSV) interconnections 2010 ·Guruprasad Katti, A. Mercha, Michele Stucchi, Zs. Tôkei, Dimitrios Velenis, J. Van Olmen, Cedric Huyghebaert, Anne Jourdain, Michał Rakowski, I. Debusschere, (unknown), Herman Oprins, Wim Dehaene, K. De Meyer, Youssef Travaly, Eric Beyne, S. Biesemans, Bart Swinnen	26
10	The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET 2009 ·VUBIR (Vrije Universiteit Brussel) ·Bertrand Parvais, A. Mercha, Nadine Collaert, R. Rooyackers, Isabelle Ferain, M. Jurczak, Vaidyanathan Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, Liesbeth Witters, S. Biesemans, T. Hoffman	29
11	Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk? 2009 ·VUBIR (Vrije Universiteit Brussel) ·T. Chiarella, Liesbeth Witters, A. Mercha, C. Kerner, R. Dittrich, Michał Rakowski, C. Ortolland, Lars‐Åke Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, Thomas Hoffmann	11
12	Schottky-Barrier Height Lowering by an Increase of the Substrate Doping in PtSi Schottky Barrier Source/Drain FETs 2007 ·IEEE Electron Device Letters ·(unknown), H.Y. Yu, (unknown), E. Augendre, A. De Keersgieter, A. Lauwers, (unknown), P. Absil, M. Jurczak, S. Biesemans	13
13	Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates 2007 ·IEEE Electron Device Letters ·Lars‐Åke Ragnarsson, Vincent S. Chang, H.Y. Yu, Hag‐Ju Cho, Thierry Conard, Kai Yin, Annelies Delabie, Johan Swerts, T. Schram, Stefan De Gendt, S. Biesemans	28
14	Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology 2006 ·Symposium on VLSI Technology ·C. Ortolland, L.-Å. Ragnarsson, Paola Favia, Olivier Richard, C. Kerner, T. Chiarella, Erik Rosseel, Y. Okuno, A. Akheyar, (unknown), (unknown), T. Schram, S. Kubicek, M. Aoulaiche, (unknown), (unknown), S. Biesemans, Thomas Hoffmann	1
15	CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON 2006 ·IEEE Electron Device Letters ·J. A. Kittl, A. Lauwers, A. Veloso, Thomas Hoffmann, Stefan Kubicek, M. Niwa, M.J.H. van Dal, Małgorzata Pawlak, S. Brus, C. Demeurisse, C. Vrancken, P. Absil, S. Biesemans	14
16	Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire 2006 ·Physical Review Letters ·H. Sellier, G. P. Lansbergen, J. Caro, Sven Rogge, Nadine Collaert, (unknown), (unknown), S. Biesemans	191
17	Integration of ultra shallow junctions in PVD TaN nMOS transistors with Flash Lamp Annealing 2005 ·S. Severi, K. De Meyer, (unknown), Ray Duffy, C. Kerner, S. McCoy, (unknown), (unknown), L.-Å. Ragnarsson, P. Absil, M. Jurczak, S. Biesemans	2
18	CMOS with active well bias for low-power and RF/analog applications 2002 ·C. Wann, James A. Harrington, (unknown), S. Biesemans, Ki Jin Han, R.H. Dennard, (unknown), (unknown), R. Mahnkopf, (unknown)	33
19	Comparison of the freeze-out effect in In and B doped n-MOSFETs in the range 4.2-300 K 1998 ·(unknown), Eddy Simoen, S. Biesemans, K. De Meyer, Cor Claeys	1
20	One junction approach to make deep submicron PMOSFETs for low power applications 1996 ·European Solid-State Device Research Conference ·Stefan Kubicek, S. Biesemans, K. De Meyer	2

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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