C.H. Diaz

3.3k total citations
109 papers, 2.2k citations indexed

About

C.H. Diaz is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Biomedical Engineering. According to data from OpenAlex, C.H. Diaz has authored 109 papers receiving a total of 2.2k indexed citations (citations by other indexed papers that have themselves been cited), including 103 papers in Electrical and Electronic Engineering, 20 papers in Atomic and Molecular Physics, and Optics and 10 papers in Biomedical Engineering. Recurrent topics in C.H. Diaz's work include Semiconductor materials and devices (78 papers), Advancements in Semiconductor Devices and Circuit Design (63 papers) and Integrated Circuits and Semiconductor Failure Analysis (29 papers). C.H. Diaz is often cited by papers focused on Semiconductor materials and devices (78 papers), Advancements in Semiconductor Devices and Circuit Design (63 papers) and Integrated Circuits and Semiconductor Failure Analysis (29 papers). C.H. Diaz collaborates with scholars based in Taiwan, United States and Mexico. C.H. Diaz's co-authors include C. Duvvury, J.-P. Colinge, Jong‐Tae Park, Sung-Mo Kang, Sung‐Mo Kang, Charvaka Duvvury, G. Doornbos, M. Passlack, G. Vellianitis and S.S. Wong and has published in prestigious journals such as Applied Physics Letters, Journal of The Electrochemical Society and IEEE Journal of Solid-State Circuits.

In The Last Decade

C.H. Diaz

105 papers receiving 2.1k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
C.H. Diaz Taiwan	27	2.1k	332	235	192	83	109	2.2k
A. Mocuta Belgium	24	2.1k 1.0×	341 1.0×	244 1.0×	214 1.1×	83 1.0×	117	2.2k
G. Shahidi United States	22	1.9k 0.9×	294 0.9×	199 0.8×	139 0.7×	111 1.3×	104	2.0k
A. Asenov United Kingdom	25	2.4k 1.1×	259 0.8×	333 1.4×	123 0.6×	168 2.0×	156	2.5k
Geert Hellings Belgium	22	1.8k 0.8×	394 1.2×	272 1.2×	242 1.3×	61 0.7×	204	2.0k
A. Spessot Belgium	19	1.5k 0.7×	223 0.7×	153 0.7×	159 0.8×	118 1.4×	113	1.6k
O. Faynot France	26	2.6k 1.2×	505 1.5×	177 0.8×	204 1.1×	120 1.4×	163	2.7k
S. Biesemans Belgium	28	2.4k 1.1×	326 1.0×	736 3.1×	278 1.4×	43 0.5×	171	2.5k
K. Asano Japan	9	2.0k 1.0×	390 1.2×	157 0.7×	181 0.9×	47 0.6×	16	2.2k
K. Mistry United States	22	2.2k 1.0×	324 1.0×	191 0.8×	177 0.9×	185 2.2×	56	2.3k
Tomohisa Mizuno Japan	22	2.1k 1.0×	608 1.8×	263 1.1×	278 1.4×	66 0.8×	126	2.2k

Countries citing papers authored by C.H. Diaz

Since Specialization

Citations

This map shows the geographic impact of C.H. Diaz's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C.H. Diaz with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C.H. Diaz more than expected).

Fields of papers citing papers by C.H. Diaz

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C.H. Diaz. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C.H. Diaz. The network helps show where C.H. Diaz may publish in the future.

Co-authorship network of co-authors of C.H. Diaz

This figure shows the co-authorship network connecting the top 25 collaborators of C.H. Diaz. A scholar is included among the top collaborators of C.H. Diaz based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C.H. Diaz. C.H. Diaz is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Diaz, C.H.. (2024). Logic Technology Device Innovations. 1–4. 2 indexed citations

Diaz, C.H., et al.. (2023). Analysis and description of crimes in Mexico city using point pattern analysis within networks. Annals of GIS. 29(2). 243–259. 3 indexed citations

Huang, Yen‐Lin, Chien‐Ming Lee, Fen Xue, et al.. (2021). Challenges toward Low-Power SOT-MRAM. 1–7. 8 indexed citations

Mukhopadhyay, Subhadeep, Win-San Khwa, P. J. Liao, et al.. (2020). Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs. 1–2. 51 indexed citations

Khwa, Win-San, et al.. (2018). A 40nm Low-Power Logic Compatible Phase Change Memory Technology. 27.6.1–27.6.4. 30 indexed citations

Li, X., S. W. Chang, T. Vasen, et al.. (2016). InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process. IEEE Electron Device Letters. 37(3). 261–264. 19 indexed citations

Wang, Shui-Jinn, et al.. (2015). Impact of SMT-induced edge dislocation positions to NFET performance. 184–184. 2 indexed citations

Rojas-Ramírez, Juan Salvador, R. Contreras‐Guerrero, M. Holland, et al.. (2015). Al In1−As Sb1− alloys lattice matched to InAs(1 0 0) grown by molecular beam epitaxy. Journal of Crystal Growth. 425. 33–38. 5 indexed citations

Huang, M. L., S. W. Chang, Cuncai Fan, et al.. (2015). In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate. T204–T205. 24 indexed citations

10.

Dal, M.J.H. van, G. Vellianitis, B. Duriez, et al.. (2014). Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping. IEEE Transactions on Electron Devices. 61(2). 430–436. 48 indexed citations

11.

Diaz, C.H., et al.. (2013). Expanding role of predictive TCAD in advanced technology development. 167–171. 10 indexed citations

12.

Doornbos, G., Krishna K. Bhuwalka, R. Contreras‐Guerrero, et al.. (2013). InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces. Applied Physics Letters. 103(14). 30 indexed citations

13.

Chang, Edward Yi, et al.. (2013). Electrical Characteristics of ${\rm Al}_{2}{\rm O}_{3}/{\rm InSb}$ MOSCAPs and the Effect of Postdeposition Annealing Temperatures. IEEE Transactions on Electron Devices. 60(5). 1555–1560. 11 indexed citations

14.

Chang, Mi-Chang, et al.. (2008). Transistor-and Circuit-Design Optimization for Low-Power CMOS. IEEE Transactions on Electron Devices. 55(1). 84–95. 25 indexed citations

15.

Chen, Chien‐Hao, Ken Goto, C.H. Diaz, et al.. (2006). Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS. 174–175. 7 indexed citations

16.

Diaz, C.H.. (2002). Bulk CMOS technology for SOC. 91–95. 1 indexed citations

17.

Diaz, C.H., et al.. (2002). An accurate analytical delay model for BiCMOS driver circuits. 33. 558–561.

18.

Wang, Chih-Chiang, et al.. (2001). Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction. IEEE Electron Device Letters. 22(2). 65–67. 38 indexed citations

19.

Liu, Huayu, C.H. Diaz, Peng Cheng, et al.. (1998). 100-nm CMOS gates patterned with 3 sigma below 10 nm. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 3331. 375–375. 2 indexed citations

20.

Diaz, C.H., et al.. (1992). Achieving uniform nMOS device power distribution for sub-micron ESD reliability. 131–134. 71 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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