S. Brus

1.2k total citations
48 papers, 492 citations indexed

About

S. Brus is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Materials Chemistry. According to data from OpenAlex, S. Brus has authored 48 papers receiving a total of 492 indexed citations (citations by other indexed papers that have themselves been cited), including 46 papers in Electrical and Electronic Engineering, 7 papers in Atomic and Molecular Physics, and Optics and 5 papers in Materials Chemistry. Recurrent topics in S. Brus's work include Semiconductor materials and devices (44 papers), Advancements in Semiconductor Devices and Circuit Design (34 papers) and Ferroelectric and Negative Capacitance Devices (15 papers). S. Brus is often cited by papers focused on Semiconductor materials and devices (44 papers), Advancements in Semiconductor Devices and Circuit Design (34 papers) and Ferroelectric and Negative Capacitance Devices (15 papers). S. Brus collaborates with scholars based in Belgium, United States and Netherlands. S. Brus's co-authors include S. Biesemans, A. Lauwers, P. Absil, A. Veloso, Naoto Horiguchi, A. De Keersgieter, Thomas Hoffmann, C. Vrancken, Stefan Kubicek and T. Chiarella and has published in prestigious journals such as Applied Physics Letters, IEEE Transactions on Electron Devices and Japanese Journal of Applied Physics.

In The Last Decade

S. Brus

45 papers receiving 476 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S. Brus Belgium 13 469 98 86 56 14 48 492
Hiroaki Arimura Belgium 15 620 1.3× 95 1.0× 82 1.0× 95 1.7× 20 1.4× 96 651
E. Dentoni Litta Belgium 12 414 0.9× 106 1.1× 53 0.6× 50 0.9× 30 2.1× 69 469
R. Kies France 10 317 0.7× 84 0.9× 33 0.4× 44 0.8× 19 1.4× 21 323
Reza Arghavani United States 12 450 1.0× 55 0.6× 60 0.7× 76 1.4× 27 1.9× 30 479
Wei Yip Loh Singapore 9 332 0.7× 68 0.7× 63 0.7× 46 0.8× 18 1.3× 27 348
A. Naem Canada 9 272 0.6× 62 0.6× 105 1.2× 40 0.7× 14 1.0× 28 311
A. St. Amour United States 10 460 1.0× 106 1.1× 196 2.3× 44 0.8× 10 0.7× 16 478
F.N. Cubaynes Belgium 9 369 0.8× 48 0.5× 34 0.4× 60 1.1× 7 0.5× 26 388
C. Kerner Belgium 11 347 0.7× 26 0.3× 63 0.7× 40 0.7× 6 0.4× 33 360
P. Charvát United States 4 390 0.8× 47 0.5× 56 0.7× 93 1.7× 9 0.6× 5 412

Countries citing papers authored by S. Brus

Since Specialization
Citations

This map shows the geographic impact of S. Brus's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Brus with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Brus more than expected).

Fields of papers citing papers by S. Brus

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Brus. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Brus. The network helps show where S. Brus may publish in the future.

Co-authorship network of co-authors of S. Brus

This figure shows the co-authorship network connecting the top 25 collaborators of S. Brus. A scholar is included among the top collaborators of S. Brus based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Brus. S. Brus is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Franco, J., Hiroaki Arimura, S. Brus, et al.. (2024). Impact of work function metal stacks on the performance and reliability of multi-V RMG CMOS technology. Solid-State Electronics. 216. 108929–108929. 1 indexed citations
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Franco, J., Hiroaki Arimura, Jean‐François de Marneffe, et al.. (2023). Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. 1–2. 1 indexed citations
5.
Franco, J., Hiroaki Arimura, Jean‐François de Marneffe, et al.. (2023). Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. IEEE Transactions on Electron Devices. 70(12). 6658–6664. 2 indexed citations
6.
Veloso, A., Geert Eneman, Bjorn Vermeersch, et al.. (2022). Insights into Scaled Logic Devices Connected from Both Wafer Sides. 2022 International Electron Devices Meeting (IEDM). 23.3.1–23.3.4. 4 indexed citations
7.
Wan, Danny, Sébastien Couet, Odysseas Zografos, et al.. (2018). Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions. HAL (Le Centre pour la Communication Scientifique Directe). 3. 36.4.1–36.4.4. 8 indexed citations
8.
Togo, M., G. Boccardi, R. Ritzenthaler, et al.. (2013). Heated implantation with amorphous Carbon CMOS mask for scaled FinFETs. Symposium on VLSI Technology. 6 indexed citations
9.
Lee, Jae Wook, M. Togo, G. Boccardi, et al.. (2013). Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors. Applied Physics Letters. 102(22). 28 indexed citations
10.
Tolle, John, Matthias Bauer, Vladimir Machkaoutsan, et al.. (2012). Orientation Dependence of Si1-xCx:P Growth and the Impact on FinFET Structures. ECS Meeting Abstracts. MA2012-02(43). 3160–3160. 1 indexed citations
11.
Sebaai, Farid, A. Veloso, Martine Claes, et al.. (2012). Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate. Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena. 187. 53–56. 3 indexed citations
12.
Chiarella, T., Liesbeth Witters, A. Mercha, et al.. (2010). Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession. Solid-State Electronics. 54(9). 855–860. 99 indexed citations
13.
Chiarella, T., Liesbeth Witters, A. Mercha, et al.. (2009). Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk?. VUBIR (Vrije Universiteit Brussel). 85–88. 11 indexed citations
14.
Chiarella, T., Liesbeth Witters, A. Mercha, et al.. (2009). Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?. VUBIR (Vrije Universiteit Brussel). 84–87. 20 indexed citations
15.
Veloso, A., M. Demand, Isabelle Ferain, et al.. (2008). Capping-metal gate integration technology for multiple-V<inf>T</inf> CMOS in MuGFETs. irps2008. 119–120. 2 indexed citations
16.
Kittl, J. A., A. Lauwers, A. Veloso, et al.. (2006). CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON. IEEE Electron Device Letters. 27(12). 966–968. 14 indexed citations
17.
Lenoble, D., A. De Keersgieter, Nadine Collaert, et al.. (2006). Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions. 168–169. 17 indexed citations
18.
Kittl, J. A., Małgorzata Pawlak, A. Lauwers, et al.. (2006). Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates. Microelectronic Engineering. 83(11-12). 2117–2121. 4 indexed citations
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Anil, K.G., A. Veloso, Stefan Kubicek, et al.. (2004). Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications. 190–191. 30 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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