S. Brus

1.2k citations

48 papers · 492 indexed · h-index 13

Impact in

Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
Atomic and Molecular Physics, and Optics
- Semiconductor materials and interfaces

Papers in ⓘ

Electrical and Electronic Engineering 46
- Semiconductor materials and devices 44
- Advancements in Semiconductor Devices and Circuit Design 34
- Ferroelectric and Negative Capacitance Devices 15
- Integrated Circuits and Semiconductor Failure Analysis 11
- Silicon and Solar Cell Technologies 4
- Advanced Memory and Neural Computing 3
Atomic and Molecular Physics, and Optics 7
- Semiconductor materials and interfaces 6

Co-authors: S. Biesemans (14 shared papers)A. Lauwers (9 shared papers)A. De Keersgieter (10 shared papers)P. Absil (11 shared papers)Naoto Horiguchi (21 shared papers)Thomas Hoffmann (10 shared papers)A. Veloso (19 shared papers)C. Vrancken (7 shared papers)
Journals: Microelectronic Engineering (3 papers)IEEE Electron Device Letters (2 papers)Japanese Journal of Applied Physics (2 papers)Solid-State Electronics (2 papers)Applied Physics Letters (1 paper)
Partner nations: Belgium United States Netherlands

In The Last Decade

S. Brus

45 papers receiving 476 citations

Peers

Countries citing papers authored by S. Brus

Since Specialization

Citations

This map shows the geographic impact of S. Brus's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Brus with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Brus more than expected).

Fields of papers citing papers by S. Brus

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Brus. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Brus. The network helps show where S. Brus may publish in the future.

Co-authors

The 25 scholars most cited alongside S. Brus, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S. Brus Line = papers co-authored together S. Brus links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 48 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Solid-State Electronics ·T. Chiarella, Liesbeth Witters, A. Mercha, C. Kerner, Michał Rakowski, C. Ortolland, (unknown), Bertrand Parvais, A. De Keersgieter, Stefan Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, Thomas Hoffmann	2010	99
2	WS<inf>2</inf> transistors on 300 mm wafers with BEOL compatibility T. Schram, Quentin Smets, Benjamin Groven, Markus Heyne, E. Kunnen, Arame Thiam, K. Devriendt, Annelies Delabie, Dennis Lin, Marcel Lux, Daniele Chiappe, Inge Asselberghs, S. Brus, Cedric Huyghebaert, Şafak Sayan, A. Juncker, Matty Caymax, Iuliana Radu	2017	39
3	Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications K.G. Anil, A. Veloso, Stefan Kubicek, T. Schram, E. Augendre, Jean‐François de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, S. Biesemans	2004	30
4	Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors Applied Physics Letters ·Jae Wook Lee, Y. Sasaki, Moon Ju Cho, M. Togo, G. Boccardi, R. Ritzenthaler, Geert Eneman, T. Chiarella, S. Brus, Naoto Horiguchi, G. Groeseneken, Aaron Thean	2013	28
5	Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lenghts J. A. Kittl, A. Veloso, A. Lauwers, K.G. Anil, C. Demeurisse, S. Kubicek, M. Niwa, M.J.H. van Dal, Olivier Richard, Małgorzata Pawlak, M. Jurczak, C. Vrancken, T. Chiarelia, S. Brus, Karen Maex, S. Baesmans	2005	21
6	Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? VUBIR (Vrije Universiteit Brussel) ·T. Chiarella, Liesbeth Witters, A. Mercha, C. Kerner, R. Dittrich, Michał Rakowski, C. Ortolland, Lars‐Åke Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, Thomas Hoffmann	2009	20
7	BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration J. Franco, Zhicheng Wu, G. Rzepa, A. Vandooren, Hiroaki Arimura, Lars‐Åke Ragnarsson, Geert Hellings, S. Brus, Daire Cott, V. De Heyn, G. Groeseneken, Naoto Horiguchi, Julien Ryckaert, Nadine Collaert, D. Linten, Tibor Grasser, B. Kaczer	2018	18
8	Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions D. Lenoble, K. Anil, A. De Keersgieter, P. Eybens, Nadine Collaert, R. Rooyackers, S. Brus, Paul Zimmerman, M. W. Goodwin, Danielle Vanhaeren, Wilfried Vandervorst, Svetlana Radovanov, Ludovic Godet, Christophe Cardinaud, S. Biesemans, T. Skotnicki, M. Jurczak	2006	17
9	A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C Nadine Collaert, M. Aoulaiche, B. De Wachter, Michał Rakowski, A. Redolfi, S. Brus, A. De Keersgieter, Naoto Horiguchi, L. Altimime, M. Jurczak	2010	15
10	Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices 2021 IEEE International Electron Devices Meeting (IEDM) ·Hiroaki Arimura, Lars‐Åke Ragnarsson, Yusuke Oniki, J. Franco, A. Vandooren, S. Brus, A. Leonhardt, P. Sippola, T. Ivanova, Giuseppe Alessio Verni, RuoFei CHANG, Qiyuan Xie, Michael Givens, Jérôme Mitard, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi	2021	15
11	CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON IEEE Electron Device Letters ·J. A. Kittl, A. Lauwers, A. Veloso, Thomas Hoffmann, Stefan Kubicek, M. Niwa, M.J.H. van Dal, Małgorzata Pawlak, S. Brus, C. Demeurisse, C. Vrancken, P. Absil, S. Biesemans	2006	14
12	Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs A. Veloso, K.G. Anil, L. Witters, S. Brus, S. Kubicek, Jean‐François de Marneffe, B. Sijmus, K. Devriendt, A. Lauwers, T. Kauerauf, M. Jurczak, S. Bieseinans	2005	13
13	Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application Gouri Sankar Kar, A. Fantini, YY Chen, Vasile Paraschiv, B. Govoreanu, Hubert Hody, N. Jossart, Hilde Tielens, S. Brus, Olivier Richard, T. Vandeweyer, Dirk J. Wouters, L. Altimime, M. Jurczak	2012	12
14	A record Gm_SAT/SS_SAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation Hiroaki Arimura, Daire Cott, G. Boccardi, Roger Loo, Kurt Wostyn, S. Brus, E. Capogreco, A. Opdebeeck, Liesbeth Witters, Thierry Conard, Samuel Suhard, Dennis H. van Dorp, Karine Kenis, L.-Å. Ragnarsson, Jérôme Mitard, Frank Holsteyns, V. De Heyn, D. Mocuta, Nadine Collaert, Naoto Horiguchi	2019	12
15	Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk? VUBIR (Vrije Universiteit Brussel) ·T. Chiarella, Liesbeth Witters, A. Mercha, C. Kerner, R. Dittrich, Michał Rakowski, C. Ortolland, Lars‐Åke Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, Thomas Hoffmann	2009	11
16	Challenges and opportunities of vertical FET devices using 3D circuit design layouts A. Veloso, Zheng Tao, W. Li, Efrain Altamirano Sánchez, Janko Versluijs, S. Brus, Philippe Matagne, Niamh Waldron, Julien Ryckaert, D. Mocuta, Nadine Collaert, Trong Huynh-Bao, Erik Rosseel, Vasile Paraschiv, K. Devriendt, E. Vecchio, Christie Delvaux, B. T. Chan, Monique Ercken	2016	11
17	Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications Japanese Journal of Applied Physics ·A. Veloso, A. De Keersgieter, S. Brus, Naoto Horiguchi, P. Absil, Thomas Hoffmann	2011	9
18	Ge oxide scavenging and gate stack nitridation for strained Si_0.7Ge_0.3 pFinFETs enabling 35% higher mobility than Si Hiroaki Arimura, Kurt Wostyn, L.-Å. Ragnarsson, E. Capogreco, Adrian Chasin, Thierry Conard, S. Brus, Paola Favia, J. Franco, Jérôme Mitard, S. Demuynck, Naoto Horiguchi	2019	9
19	Modulation of the effective work function of fully-silicided (FUSI) gate stacks Microelectronic Engineering ·J. A. Kittl, A. Lauwers, Małgorzata Pawlak, A. Veloso, H.Y. Yu, S.Z. Chang, Thomas Hoffmann, Geoffrey Pourtois, S. Brus, C. Demeurisse, C. Vrancken, P. Absil, S. Biesemans	2007	9
20	Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions HAL (Le Centre pour la Communication Scientifique Directe) ·Eline Raymenants, Danny Wan, Sébastien Couet, Odysseas Zografos, V.D. Nguyen, Adrien Vaysset, Laurent Souriau, Arame Thiam, Mauricio Manfrini, S. Brus, Marc Heyns, D. Mocuta, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young, T. Devolder, Iuliana Radu	2018	8

About S. Brus

S. Brus is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Electronic, Optical and Magnetic Materials, Materials Chemistry and Biomedical Engineering, having authored 48 papers that have together received 492 indexed citations. Recurring topics across this work include Semiconductor materials and devices (44 papers), Advancements in Semiconductor Devices and Circuit Design (34 papers), Ferroelectric and Negative Capacitance Devices (15 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers), Semiconductor materials and interfaces (6 papers), Silicon and Solar Cell Technologies (4 papers), Silicon Nanostructures and Photoluminescence (3 papers) and Advanced Memory and Neural Computing (3 papers). The work is most often cited by research in Electrical and Electronic Engineering (469 citations), Atomic and Molecular Physics, and Optics (86 citations), Materials Chemistry (98 citations), Biomedical Engineering (56 citations) and Hardware and Architecture (8 citations). S. Brus has collaborated with scholars based in Belgium, United States and Netherlands. Frequent co-authors include S. Biesemans, A. Lauwers, A. De Keersgieter, P. Absil, Naoto Horiguchi, Thomas Hoffmann, A. Veloso, C. Vrancken, T. Chiarella and Stefan Kubicek. Their work appears in journals such as Microelectronic Engineering, IEEE Electron Device Letters, Japanese Journal of Applied Physics, Solid-State Electronics and Applied Physics Letters.

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