M. Cho

650 citations

24 papers · 457 indexed · h-index 12

Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices 23
- Advancements in Semiconductor Devices and Circuit Design 20
- Integrated Circuits and Semiconductor Failure Analysis 16
- Ferroelectric and Negative Capacitance Devices 4
- Advanced Memory and Neural Computing 2
Hardware and Architecture
Materials Chemistry
- Electronic and Structural Properties of Oxides 2
Condensed Matter Physics
Electronic, Optical and Magnetic Materials
Building and Construction
- Building Energy and Comfort Optimization 1
Mechanical Engineering
- Refrigeration and Air Conditioning Technologies 1

Co-authors: B. Kaczer G. Groeseneken R. Degraeve Ph. Roussel J. Franco M. B. Zahid Tibor Grasser T. Kauerauf
Cited by: Electrical and Electronic Engineering Hardware and Architecture Materials Chemistry
Journals: Microelectronic Engineering (3 papers)IEEE Electron Device Letters (1 paper)Solid-State Electronics (1 paper)
Partner nations: Belgium Austria United States

In The Last Decade

M. Cho

24 papers receiving 444 citations

Peers

Countries citing papers authored by M. Cho

Since Specialization

Citations

This map shows the geographic impact of M. Cho's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Cho with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Cho more than expected).

Fields of papers citing papers by M. Cho

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Cho. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Cho. The network helps show where M. Cho may publish in the future.

Co-authorship network

The 25 scholars most cited alongside M. Cho, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with M. Cho Line = papers co-authored together M. Cho links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits Solid-State Electronics ·B. Kaczer,J. Franco,Pieter Weckx,Ph. Roussel,Marko Simicic,V. Putcha,E. Bury,M. Cho,R. Degraeve,D. Linten,G. Groeseneken,Peter Debacker,Bertrand Parvais,Prasanth Raghavan,Francky Catthoor,G. Rzepa,Michael Waltl,Wolfgang Goes,Tibor Grasser	2016	18
2	On and off state hot carrier reliability in junctionless high-K MG gate-all-around nanowires M. Cho,Geert Hellings,A. Veloso,Eddy Simoen,Ph. Roussel,B. Kaczer,Hiroaki Arimura,Wen Fang,J. Franco,Philippe Matagne,Nadine Collaert,D. Linten,Aaron Thean	2015	11
3	The defect-centric perspective of device and circuit reliability — From individual defects to circuits B. Kaczer,J. Franco,Pieter Weckx,Ph. Roussel,E. Bury,M. Cho,R. Degraeve,D. Linten,G. Groeseneken,Halil Kükner,Prasanth Raghavan,Francky Catthoor,G. Rzepa,Wolfgang Goes,Tibor Grasser	2015	16
4	BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities G. Groeseneken,J. Franco,M. Cho,B. Kaczer,M. Toledano-Luque,Ph. Roussel,T. Kauerauf,A. Alian,Jérôme Mitard,Hiroaki Arimura,Dennis Lin,Niamh Waldron,Sonja Sioncke,Liesbeth Witters,Hans Mertens,Lars‐Åke Ragnarsson,Marc Heyns,Nadine Collaert,Aaron Thean,An Steegen	2014	30
5	Degradation of time dependent variability due to interface state generation Symposium on VLSI Technology ·M. Toledano-Luque,B. Kaczer,J. Franco,Ph. Roussel,M. Bina,Tibor Grasser,M. Cho,Pieter Weckx,G. Groeseneken	2013	41
6	Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions G. Groeseneken,M. Aoulaiche,M. Cho,J. Franco,B. Kaczer,T. Kauerauf,Jérôme Mitard,Lars‐Åke Ragnarsson,Philippe Roussel,M. Toledano-Luque	2013	5
7	Superior reliability of high mobility (Si)Ge channel pMOSFETs Microelectronic Engineering ·J. Franco,B. Kaczer,M. Toledano-Luque,Ph. Roussel,M. Cho,T. Kauerauf,Jérôme Mitard,Geert Eneman,Liesbeth Witters,Tibor Grasser,G. Groeseneken	2013	1
8	Experimental Study on Fault Detection Algorithm Using Regression Method for Plural Indoor Units Faults of Multi-Heat Pump System under Heating Mode Purdue e-Pubs (Purdue University System) ·Hak Soo Kim,M. Cho,Min Soo Kim	2012	5
9	Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications J. Franco,B. Kaczer,Jérôme Mitard,M. Toledano-Luque,Felice Crupi,Geert Eneman,M Niewald,Tibor Grasser,M. Cho,T. Kauerauf,Liesbeth Witters,Geert Hellings,L.-Å. Ragnarsson,Naoto Horiguchi,Marc Heyns,G. Groeseneken	2012	4
10	Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, FinFETs, and impact of Body Bias J. Franco,B. Kaczer,Geert Eneman,Ph. Roussel,Tibor Grasser,Jérôme Mitard,Lars‐Åke Ragnarsson,M. Cho,Liesbeth Witters,T. Chiarella,M. Togo,Boyang Cui,Andriy Hikavyy,Roger Loo,Naoto Horiguchi,G. Groeseneken	2011	32
11	On the recoverable and permanent components of Hot Carrier and NBTI in Si pMOSFETs and their implications in Si<inf>0.45</inf>Ge<inf>0.55</inf> pMOSFETs J. Franco,B. Kaczer,Geert Eneman,Ph. Roussel,M. Cho,Jérôme Mitard,Liesbeth Witters,T. Y. Hoffmann,G. Groeseneken,Felice Crupi,Tibor Grasser	2011	10
12	Detailed analysis of charge pumping and IdVg hysteresis for profiling traps in SiO2/HfSiO(N) Microelectronic Engineering ·د محمد محمود عيسى .,R. Degraeve,M. Cho,Kris De Brabanter,Ph. Roussel,M. B. Zahid,G. Groeseneken	2010	4
13	6Å EOT Si<inf>0.45</inf>Ge<inf>0.55</inf> pMOSFET with optimized reliability (V<inf>DD</inf>=1V): Meeting the NBTI lifetime target at ultra-thin EOT J. Franco,B. Kaczer,Geert Eneman,Jérôme Mitard,A. Stesmans,V. V. Afanas’ev,T. Kauerauf,Ph. Roussel,M. Toledano-Luque,M. Cho,R. Degraeve,Tibor Grasser,Lars‐Åke Ragnarsson,Liesbeth Witters,P Cacciatori,Shinji Takeoka,Aldy Renaldy,T. Y. Hoffmann,G. Groeseneken	2010	13
14	Interpretation of PBTI/ TDDB predicted lifetime based on trap characterization by TSCIS in V<inf>th</inf>-adjusted transistors د محمد محمود عيسى .,R. Degraeve,C. Ebeling,M. Cho,T. Kauerauf,G. Groeseneken	2010	1
15	Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory Microelectronic Engineering ·B. Govoreanu,R. Degraeve,M. B. Zahid,Laura Nyns,M. Cho,B. Kaczer,M. Jurczak,J. A. Kittl,Jan Van Houdt	2009	17
16	Deffect profiling in the SiO<inf>2</inf>/ Al<inf>2</inf>O<inf>3</inf> interface using Variable T<inf>charge</inf>-T<inf>discharge</inf> Amplitude Charge Pumping (VT<sup>2</sup>ACP) M. B. Zahid,R. Degraeve,M. Cho,L. Pantisano,Adenugbe A Vormawor,Jan Van Houdt,G. Groeseneken,M. Jurczak	2009	4
17	Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks R. Degraeve,M. Cho,B. Govoreanu,B. Kaczer,M. B. Zahid,Jan Van Houdt,M. Jurczak,G. Groeseneken	2008	86
18	Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress R. Degraeve,T. Kauerauf,M. Cho,M. Zahid,L.-Å. Ragnarsson,D.P. Brunco,B. Kaczer,Ph. Roussel,Stefan De Gendt,G. Groeseneken	2006	57
19	Explaining `Voltage-Driven' Breakdown Statistics by Accurately Modeling Leakage Current Increase in Thin SiON and SiO2/High-K Stacks R. Degraeve,Ph. Roussel,M. Cho,B. Kaczer,T. Kauerauf,Felice Crupi,G. Groeseneken	2006	11
20	Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation? IEEE Electron Device Letters ·T. Kauerauf,R. Degraeve,M. B. Zahid,M. Cho,B. Kaczer,Ph. Roussel,G. Groeseneken,H.E. Maes,Stefan De Gendt	2005	28

About M. Cho

M. Cho is a scholar working on Electrical and Electronic Engineering, Bioengineering, Building and Construction, Materials Chemistry and Mechanical Engineering, having authored 24 papers that have together received 457 indexed citations. Recurring topics across this work include Semiconductor materials and devices (23 papers), Advancements in Semiconductor Devices and Circuit Design (20 papers), Integrated Circuits and Semiconductor Failure Analysis (16 papers), Ferroelectric and Negative Capacitance Devices (4 papers), Advanced Memory and Neural Computing (2 papers), Electronic and Structural Properties of Oxides (2 papers), Building Energy and Comfort Optimization (1 paper) and Refrigeration and Air Conditioning Technologies (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (446 citations), Hardware and Architecture (9 citations), Materials Chemistry (50 citations), Condensed Matter Physics (12 citations) and Electronic, Optical and Magnetic Materials (18 citations). M. Cho has collaborated with scholars based in Belgium, Austria and United States. Frequent co-authors include B. Kaczer, G. Groeseneken, R. Degraeve, Ph. Roussel, J. Franco, M. B. Zahid, Tibor Grasser, T. Kauerauf, B. Govoreanu and Jan Van Houdt. Their work appears in journals such as Microelectronic Engineering, IEEE Electron Device Letters, Solid-State Electronics, Purdue e-Pubs (Purdue University System) and Symposium on VLSI Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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