Countries citing papers authored by Geert Hellings
Since
Specialization
Citations
This map shows the geographic impact of Geert Hellings's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Geert Hellings with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Geert Hellings more than expected).
This network shows the impact of papers produced by Geert Hellings. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Geert Hellings. The network helps show where Geert Hellings may publish in the future.
Co-authorship network of co-authors of Geert Hellings
This figure shows the co-authorship network connecting the top 25 collaborators of Geert Hellings.
A scholar is included among the top collaborators of Geert Hellings based on the total number of
citations received by their joint publications. Widths of edges
represent the number of papers authors have co-authored together.
Node borders
signify the number of papers an author published with Geert Hellings. Geert Hellings is excluded from
the visualization to improve readability, since they are connected to all nodes in the network.
Linten, Dimitri, Geert Hellings, Shih‐Hung Chen, et al.. (2013). ESD performance of high mobility SiGe quantum well bulk finFET diodes and PMOS devices. Electrical Overstress/Electrostatic Discharge Symposium. 1–8.4 indexed citations
15.
Scholz, Mirko, Shih‐Hung Chen, Geert Hellings, & Dimitri Linten. (2013). Impact of the on-chip and off-chip ESD protection network on transient-induced latch-up in CMOS IC. Electrical Overstress/Electrostatic Discharge Symposium. 1–7.5 indexed citations
16.
Chen, Shih‐Hung, S. Thijs, Dimitri Linten, et al.. (2012). ESD protection devices placed inside keep-out zone (KOZ) of through Silicon Via (TSV) in 3D stacked integrated circuits. Electrical Overstress/Electrostatic Discharge Symposium. 1–8.12 indexed citations
17.
Hellings, Geert, Dimitri Linten, S. Thijs, et al.. (2012). ESD characterization of high mobility SiGe Quantum Well and Ge devices for future CMOS scaling. Electrical Overstress/Electrostatic Discharge Symposium. 1–6.5 indexed citations
18.
Scholz, Mirko, Geert Hellings, D. Linten, et al.. (2012). Miscorrelation between IEC61000-4-2 type of HMM tester and 50 Ω HMM tester. Electrical Overstress/Electrostatic Discharge Symposium. 1–9.2 indexed citations
19.
Hellings, Geert, Geert Eneman, Brice De Jaeger, et al.. (2009). Scalability of quantum well devices for digital logic applications. 33–34.2 indexed citations
20.
Mitard, Jérôme, Michel Houssa, Geert Eneman, et al.. (2006). Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI. Symposium on VLSI Technology. 82–83.35 indexed citations
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive
bibliographic database. While OpenAlex provides broad and valuable coverage of the global
research landscape, it—like all bibliographic datasets—has inherent limitations. These include
incomplete records, variations in author disambiguation, differences in journal indexing, and
delays in data updates. As a result, some metrics and network relationships displayed in
Rankless may not fully capture the entirety of a scholar's output or impact.