A. Mallik

813 total citations
23 papers, 481 citations indexed

About

A. Mallik is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, A. Mallik has authored 23 papers receiving a total of 481 indexed citations (citations by other indexed papers that have themselves been cited), including 21 papers in Electrical and Electronic Engineering, 4 papers in Hardware and Architecture and 3 papers in Computer Networks and Communications. Recurrent topics in A. Mallik's work include Advanced Memory and Neural Computing (9 papers), Semiconductor materials and devices (9 papers) and Ferroelectric and Negative Capacitance Devices (8 papers). A. Mallik is often cited by papers focused on Advanced Memory and Neural Computing (9 papers), Semiconductor materials and devices (9 papers) and Ferroelectric and Negative Capacitance Devices (8 papers). A. Mallik collaborates with scholars based in Belgium, United States and India. A. Mallik's co-authors include Julien Ryckaert, Diederik Verkest, Peter Debacker, A. Mocuta, Gokhan Memik, D. Mocuta, Yasser Sherazi, Pieter Weckx, P. Schuddinck and Hans Mertens and has published in prestigious journals such as Journal of Alloys and Compounds, IEEE Transactions on Electron Devices and VUBIR (Vrije Universiteit Brussel).

In The Last Decade

A. Mallik

22 papers receiving 466 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
A. Mallik Belgium 11 438 61 47 43 41 23 481
Jui-Jen Wu Taiwan 11 416 0.9× 77 1.3× 27 0.6× 24 0.6× 20 0.5× 20 428
Renzhi Liu United States 11 436 1.0× 149 2.4× 56 1.2× 53 1.2× 31 0.8× 29 487
Chien-Chen Lin Taiwan 10 387 0.9× 141 2.3× 18 0.4× 29 0.7× 19 0.5× 14 432
Arman Kazemi United States 12 381 0.9× 65 1.1× 23 0.5× 93 2.2× 66 1.6× 20 430
Jean-Philippe Noël France 12 520 1.2× 103 1.7× 54 1.1× 20 0.5× 9 0.2× 40 539
Liang Yan China 5 214 0.5× 50 0.8× 18 0.4× 43 1.0× 21 0.5× 13 271
Jiyang Kang China 8 248 0.6× 58 1.0× 24 0.5× 21 0.5× 104 2.5× 19 348
Sumitha George United States 12 506 1.2× 46 0.8× 45 1.0× 20 0.5× 118 2.9× 34 524
Gicheol Shin South Korea 9 269 0.6× 47 0.8× 42 0.9× 13 0.3× 71 1.7× 17 299
Sung-Joo Hong South Korea 10 418 1.0× 130 2.1× 16 0.3× 29 0.7× 34 0.8× 17 473

Countries citing papers authored by A. Mallik

Since Specialization
Citations

This map shows the geographic impact of A. Mallik's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Mallik with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Mallik more than expected).

Fields of papers citing papers by A. Mallik

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Mallik. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Mallik. The network helps show where A. Mallik may publish in the future.

Co-authorship network of co-authors of A. Mallik

This figure shows the co-authorship network connecting the top 25 collaborators of A. Mallik. A scholar is included among the top collaborators of A. Mallik based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with A. Mallik. A. Mallik is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
2.
Ragnarsson, L.-Å., M. Garcia Bardon, Pieter Wuytens, et al.. (2022). Environmental Impact of CMOS Logic Technologies. 82–84. 10 indexed citations
3.
Garello, Kévin, Siddharth Rao, Faisal Mohd-Yasin, et al.. (2021). Multi-pillar SOT-MRAM for Accurate Analog in-Memory DNN Inference. Symposium on VLSI Technology. 1–2. 7 indexed citations
4.
Papistas, Ioannis A., et al.. (2021). Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. 1–4. 9 indexed citations
5.
Bardon, M. Garcia, Pieter Wuytens, L.-Å. Ragnarsson, et al.. (2020). DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies. 41.4.1–41.4.4. 55 indexed citations
6.
Cosemans, Stefan, Manu Perumkunnil, Ioannis A. Papistas, et al.. (2020). IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge. IEEE Transactions on Electron Devices. 67(11). 4616–4620. 19 indexed citations
7.
Mallik, A., Julien Ryckaert, Peter Debacker, et al.. (2019). Economics of semiconductor scaling - a cost analysis for advanced technology node. T202–T203. 4 indexed citations
8.
Cosemans, Stefan, Bram-Ernst Verhoef, Ioannis A. Papistas, et al.. (2019). Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing – A Circuit Blueprint, Device Options and Requirements. 22.2.1–22.2.4. 45 indexed citations
9.
Ryckaert, Julien, P. Schuddinck, Pieter Weckx, et al.. (2018). The Complementary FET (CFET) for CMOS scaling beyond N3. 141–142. 147 indexed citations
10.
Matagne, Philippe, Hiroaki Nakamura, Yoshiaki Kikuchi, et al.. (2018). DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM. 45–48. 3 indexed citations
11.
Degraeve, R., A. Mallik, Daniele Garbin, et al.. (2018). Opportunities and Challenges of Resistive RAM for Neuromorphic Applications. 2018. 1–5. 2 indexed citations
12.
Verkest, Diederik, Dimitrios Rodopoulos, Bram-Ernst Verhoef, et al.. (2018). Using (emerging) memories for machine learning hardware. 1 indexed citations
13.
Mallik, A., A. Vandooren, Liesbeth Witters, et al.. (2017). The impact of sequential-3D integration on semiconductor scaling roadmap. VUBIR (Vrije Universiteit Brussel). 35 indexed citations
14.
Mallik, A., Daniele Garbin, A. Fantini, et al.. (2017). Design-technology co-optimization for OxRRAM-based synaptic processing unit. T178–T179. 23 indexed citations
15.
Yakimets, Dmitry, Doyoung Jang, Prasanth Raghavan, et al.. (2015). Lateral NWFET optimization for beyond 7nm nodes. 1–4. 12 indexed citations
16.
Schuddinck, P., Mustafa Badaroglu, Michele Stucchi, et al.. (2012). Standard cell level parasitics assessment in 20nm BPL and 14nm BFF. 25.3.1–25.3.4. 8 indexed citations
17.
Ronse, Kurt, Peter De Bisschop, Geert Vandenberghe, et al.. (2012). Opportunities and challenges in device scaling by the introduction of EUV lithography. 8322. 18.5.1–18.5.4. 19 indexed citations
18.
Mallik, A., Debjit Sinha, P. Banerjee, & Hai Zhou. (2006). Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment. 1–6. 4 indexed citations
19.
Memik, Gokhan, Masud H. Chowdhury, A. Mallik, & Yehea Ismail. (2005). Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. 770–779. 26 indexed citations
20.
Mallik, A., et al.. (2004). Measuring application error rates for network processors. 2. II_521–II_524.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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