Walker J. Turner

477 citations

23 papers · 313 · h-index 8

Impact in

Hardware and Architecture top 10%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering
- Advancements in PLL and VCO Technologies
- VLSI and FPGA Design Techniques
- Low-power high-performance VLSI design
- Photonic and Optical Devices
- Advanced Memory and Neural Computing
- 3D IC and TSV technologies
- Radio Frequency Integrated Circuit Design

Papers in

Electrical and Electronic Engineering 23
- 3D IC and TSV technologies 8
- Radio Frequency Integrated Circuit Design 6
- VLSI and FPGA Design Techniques 6
- Advancements in PLL and VCO Technologies 6
- Semiconductor Lasers and Optical Devices 5
- Low-power high-performance VLSI design 4
- Wireless Power Transfer Systems 4
Hardware and Architecture 7
- VLSI and Analog Circuit Testing 5

Co-authors: Haoxing Ren (6 shared papers)C. Thomas Gray (13 shared papers)Stephen G. Tell (11 shared papers)John Wilson (11 shared papers)John W. Poulton (11 shared papers)Brian Zimmer (11 shared papers)William J. Dally (9 shared papers)Nikola Nedovic (9 shared papers)
Journals: IEEE Journal of Solid-State Circuits (5 papers)IEEE Solid-State Circuits Magazine (1 paper)RSC Advances (1 paper)2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (1 paper)2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (1 paper)
Partner nations: United States

In The Last Decade

Walker J. Turner

23 papers receiving 310 citations

Peers

Countries citing papers authored by Walker J. Turner

Since Specialization

Citations

This map shows the geographic impact of Walker J. Turner's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Walker J. Turner with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Walker J. Turner more than expected).

Fields of papers citing papers by Walker J. Turner

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Walker J. Turner. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Walker J. Turner. The network helps show where Walker J. Turner may publish in the future.

Co-authors

The 25 scholars most cited alongside Walker J. Turner, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Walker J. Turner Line = papers co-authored together Walker J. Turner links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 23 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku	2020	66
2	A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator IEEE Journal of Solid-State Circuits ·John W. Poulton, John Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, C. Thomas Gray, William J. Dally	2018	51
3	A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator John Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, C. Thomas Gray, William J. Dally	2018	34
4	Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren	2021	28
5	A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS IEEE Journal of Solid-State Circuits ·Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John Wilson, William J. Dally, C. Thomas Gray	2023	24
6	Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects Walker J. Turner, John W. Poulton, John Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray	2018	21
7	A microfluidic wireless power system RSC Advances ·Nathan Lazarus, Christopher Meyer, Walker J. Turner	2015	15
8	Reinforcement Learning Guided Detailed Routing for Custom Circuits Hao Chen, Kai–Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren	2023	9
9	A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET Sanquan Song, John W. Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John Wilson, C. Thomas Gray, William J. Dally	2019	7
10	An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop IEEE Journal of Solid-State Circuits ·Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Jih-Ren Goh, C. Thomas Gray	2022	7
11	A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John Wilson, William J. Dally, C. Thomas Gray	2022	7
12	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS IEEE Journal of Solid-State Circuits ·Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John Wilson, William J. Dally, C. Thomas Gray	2023	6
13	Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) ·Hao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren	2022	5
14	AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren	2022	5
15	TAG Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren	2022	5
16	Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John Wilson, William J. Dally, C. Thomas Gray	2024	4
17	6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John Wilson, C. Thomas Gray	2020	4
18	A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Giant Goh, C. Thomas Gray	2021	3
19	Ground-Referenced Single-Ended Signaling: Applications for High-Density, Short-Haul Communication Systems IEEE Solid-State Circuits Magazine ·John Wilson, Walker J. Turner, John W. Poulton	2019	3
20	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John Wilson, William J. Dally, C. Thomas Gray	2023	3

About Walker J. Turner

Walker J. Turner is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Automotive Engineering and Biomedical Engineering, having authored 23 papers that have together received 313 indexed citations. Recurring topics across this work include 3D IC and TSV technologies (8 papers), Radio Frequency Integrated Circuit Design (6 papers), VLSI and FPGA Design Techniques (6 papers), Advancements in PLL and VCO Technologies (6 papers), Semiconductor Lasers and Optical Devices (5 papers), VLSI and Analog Circuit Testing (5 papers), Low-power high-performance VLSI design (4 papers) and Wireless Power Transfer Systems (4 papers). The work is most often cited by research in Hardware and Architecture (78 citations), Electrical and Electronic Engineering (267 citations), Artificial Intelligence (39 citations), Computer Networks and Communications (25 citations) and Computer Vision and Pattern Recognition (21 citations). Walker J. Turner has collaborated with scholars based in United States. Frequent co-authors include Haoxing Ren, C. Thomas Gray, Stephen G. Tell, John Wilson, John W. Poulton, Brian Zimmer, William J. Dally, Nikola Nedovic, Sudhir S. Kudva and David Z. Pan. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Magazine, RSC Advances, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) and 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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