Debjit Sinha

539 total citations
37 papers, 425 citations indexed

About

Debjit Sinha is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Debjit Sinha has authored 37 papers receiving a total of 425 indexed citations (citations by other indexed papers that have themselves been cited), including 32 papers in Electrical and Electronic Engineering, 22 papers in Hardware and Architecture and 9 papers in Biomedical Engineering. Recurrent topics in Debjit Sinha's work include Low-power high-performance VLSI design (31 papers), VLSI and FPGA Design Techniques (21 papers) and VLSI and Analog Circuit Testing (13 papers). Debjit Sinha is often cited by papers focused on Low-power high-performance VLSI design (31 papers), VLSI and FPGA Design Techniques (21 papers) and VLSI and Analog Circuit Testing (13 papers). Debjit Sinha collaborates with scholars based in United States, India and Portugal. Debjit Sinha's co-authors include Hai Zhou, Narendra Shenoy, Gokhan Memik, Jonathan Adams, Hai Zhou, Jin Hu, N. Venkateswaran, Prithviraj Banerjee, Arindam Mallik and Kerim Kalafala and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design.

In The Last Decade

Debjit Sinha

33 papers receiving 398 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Debjit Sinha United States	11	348	281	64	27	27	37	425
M. d'Abreu United States	11	225 0.6×	197 0.7×	53 0.8×	31 1.1×	25 0.9×	33	302
Rob Aitken United States	6	356 1.0×	190 0.7×	104 1.6×	19 0.7×	42 1.6×	20	451
Wing-Kai Chow Hong Kong	14	484 1.4×	323 1.1×	67 1.0×	16 0.6×	18 0.7×	25	523
George Economakos Greece	9	141 0.4×	216 0.8×	97 1.5×	40 1.5×	16 0.6×	73	289
Peeter Ellervee Estonia	10	216 0.6×	367 1.3×	227 3.5×	27 1.0×	20 0.7×	94	474
Yiu-Chung Wong United States	6	399 1.1×	280 1.0×	116 1.8×	18 0.7×	8 0.3×	11	457
Milovan Blagojević United States	10	237 0.7×	143 0.5×	83 1.3×	7 0.3×	51 1.9×	12	320
John M. Emmert United States	13	445 1.3×	415 1.5×	71 1.1×	7 0.3×	30 1.1×	39	542
Ismail Bustany United States	11	430 1.2×	306 1.1×	44 0.7×	16 0.6×	7 0.3×	24	468
Florian Kriebel Germany	16	489 1.4×	333 1.2×	225 3.5×	23 0.9×	20 0.7×	38	608

Countries citing papers authored by Debjit Sinha

Since Specialization

Citations

This map shows the geographic impact of Debjit Sinha's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Debjit Sinha with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Debjit Sinha more than expected).

Fields of papers citing papers by Debjit Sinha

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Debjit Sinha. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Debjit Sinha. The network helps show where Debjit Sinha may publish in the future.

Co-authorship network of co-authors of Debjit Sinha

This figure shows the co-authorship network connecting the top 25 collaborators of Debjit Sinha. A scholar is included among the top collaborators of Debjit Sinha based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Debjit Sinha. Debjit Sinha is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Sinha, Debjit, et al.. (2021). Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. 1558–1563.

2.

Sinha, Debjit, et al.. (2020). Statistical Timing Analysis considering Multiple-Input Switching. 1–6. 4 indexed citations

3.

Sinha, Debjit, et al.. (2016). Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. 493–498. 1 indexed citations

4.

Huang, Tsung‐Wei, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, & N. Venkateswaran. (2016). A distributed timing analysis framework for large designs. 1–6. 24 indexed citations

5.

Sinha, Debjit, et al.. (2016). Generation and use of statistical timing macro-models considering slew and load variability. 1–6. 1 indexed citations

6.

Sinha, Debjit, et al.. (2016). Practical statistical static timing analysis with current source models. 1–6. 2 indexed citations

7.

Hu, Jin, et al.. (2014). TAU 2014 contest on removing common path pessimism during timing analysis. International Conference on Computer Aided Design. 591–591. 1 indexed citations

8.

Hu, Jin, et al.. (2014). TAU 2014 contest on removing common path pessimism during timing analysis. 153–160. 29 indexed citations

9.

Sinha, Debjit, et al.. (2013). TAU 2013 variation aware timing analysis contest. 171–178. 9 indexed citations

10.

Sinha, Debjit, et al.. (2012). Reversible Statistical max/min Operation: Theory and Applications to Timing. 1 indexed citations

11.

Sinha, Debjit, Chandu Visweswariah, N. Venkateswaran, Jinjun Xiong, & Vladimir Zolotov. (2012). Reversible statistical max/min operation. 1067–1073. 7 indexed citations

12.

Sinha, Debjit, et al.. (2009). A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Microprocessor Designs. 4 indexed citations

13.

Sinha, Debjit, Hai Zhou, & Narendra Shenoy. (2007). Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26(8). 1522–1533. 37 indexed citations

14.

Sinha, Debjit, et al.. (2006). Advances in Computation of the Maximum of a Set of Random Variables. 306–311. 18 indexed citations

15.

Mallik, A., Debjit Sinha, P. Banerjee, & Hai Zhou. (2006). Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment. 1–6. 4 indexed citations

16.

Sinha, Debjit, et al.. (2006). Yield-Aware Cache Architectures. 15–25. 90 indexed citations

17.

Sinha, Debjit, Narendra Shenoy, & Hai Zhou. (2005). Statistical gate sizing for timing yield optimization. 1037–1042. 39 indexed citations

18.

Sinha, Debjit & Hai Zhou. (2005). Yield driven gate sizing for coupling-noise reduction under uncertainty. 192–192. 5 indexed citations

19.

Sinha, Debjit & Hai Zhou. (2005). A unified framework for statistical timing analysis with coupling and multiple input switching. 837–843. 14 indexed citations

20.

Sinha, Debjit & Hai Zhou. (2005). Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. 14–19. 20 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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