P. Schuddinck

2.3k citations

55 papers · 1.5k indexed · h-index 20

Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices 50
- Advancements in Semiconductor Devices and Circuit Design 47
- Low-power high-performance VLSI design 16
- Ferroelectric and Negative Capacitance Devices 16
- Integrated Circuits and Semiconductor Failure Analysis 10
- Advancements in Photolithography Techniques 3
- 3D IC and TSV technologies 3
Hardware and Architecture top 5%
Biomedical Engineering top 10%
- Nanowire Synthesis and Applications 3
Materials Chemistry
Atomic and Molecular Physics, and Optics

Co-authors: Diederik Verkest Doyoung Jang Dmitry Yakimets M. Garcia Bardon Julien Ryckaert A. Mocuta Pieter Weckx Geert Eneman
Cited by: Electrical and Electronic Engineering Hardware and Architecture Biomedical Engineering
Journals: IEEE Transactions on Electron Devices (8 papers)IEEE Electron Device Letters (1 paper)Journal of Micro/Nanolithography MEMS and MOEMS (1 paper)
Partner nations: Belgium United States France

In The Last Decade

P. Schuddinck

54 papers receiving 1.4k citations

Peers

Countries citing papers authored by P. Schuddinck

Since Specialization

Citations

This map shows the geographic impact of P. Schuddinck's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Schuddinck with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Schuddinck more than expected).

Fields of papers citing papers by P. Schuddinck

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Schuddinck. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Schuddinck. The network helps show where P. Schuddinck may publish in the future.

Co-authorship network

The 25 scholars most cited alongside P. Schuddinck, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with P. Schuddinck Line = papers co-authored together P. Schuddinck links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height IEEE Journal of the Electron Devices Society ·Sérgio Luiz Francisco,P. Schuddinck,Krishna K. Bhuwalka,G. Rzepa,Gioele Mirabelli,Anshul Gupta,Juergen Boemmels,Philippe Matagne,Dmitry Yakimets,Angélica Mendes,Šárka Honová,Geert Hellings,K Navrátil	2024	1
2	DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance Sérgio Luiz Francisco,P. Schuddinck,Krishna K. Bhuwalka,G. Rzepa,Gioele Mirabelli,Philippe Matagne,Dmitry Yakimets,Hao Wu,Geert Hellings,Ali Zare Mehrjardi	2024	3
3	CMOS Scaling by Nanosheet Device Architectures and Backside Engineering Lirias (KU Leuven) ·Naoto Horiguchi,Hans Mertens,R. Ritzenthaler,S. Subramanian,Pieter Weckx,P. Schuddinck,A. Veloso,Sheng Yang,Rui Jing Li,Julien Ryckaert	2024	3
4	Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect IEEE Transactions on Circuits and Systems I Regular Papers ·E.B. Venus,M. Nivetha,Shairfe Muhammad Salahuddin,Constance Shirley,P. Schuddinck,Yang Xiang,Pieter Weckx,Geert Hellings,M. Garcia Bardon,Julien Ryckaert,Chenyun Pan,Subhasish Mitra,Francky Catthoor	2024	3
5	CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark IEEE Transactions on Electron Devices ·E.B. Venus,P. Schuddinck,Constance Shirley,Fahd Al-Amri,Hans Mertens,Shairfe Muhammad Salahuddin,Gaspard Hiblot,Yang Xiang,Boon Teik Chan,Qing Chen,Pieter Weckx,Geert Hellings,M. Garcia Bardon,Julien Ryckaert,Chenyun Pan,Francky Catthoor	2023	8
6	Design-technology co-optimization overview of CFET architecture Gioele Mirabelli,P. Schuddinck,E.B. Venus,Sheng Yang,Odysseas Zografos,Shairfe Muhammad Salahuddin,敏明中丸,Gaspard Hiblot,Geert Hellings,Julien Ryckaert	2023	4
7	Cost analysis of device options and scaling boosters below the A14 technology node Gioele Mirabelli,A. Vandooren,Adel Alaa El-din Habib,Shuichi Matsunari,Hans Mertens,SU Li-Cheng,P. Schuddinck,Gayle Murdoch,Shairfe Muhammad Salahuddin,Odysseas Zografos,L.-Å. Ragnarsson,Pieter Weckx,Zsolt Tökei,Geert Hellings,Julien Ryckaert	2023	3
8	PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology Sheng Yang,P. Schuddinck,М. І. Фатула,Yang Xiang,A. Veloso,Chih-Peng Kao,Gioele Mirabelli,Gaspard Hiblot,Geert Hellings,Julien Ryckaert	2023	17
9	DTCO of sequential and monolithic CFET SRAM E.B. Venus,Shairfe Muhammad Salahuddin,Boon Teik Chan,P. Schuddinck,Pankaj Khot,敏明中丸,Geert Hellings,Francky Catthoor	2023	5
10	PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·P. Schuddinck,F. M. Bufler,Yang Xiang,SU Li-Cheng,Gioele Mirabelli,A. Vandooren,Bilal Chehab,Anshul Gupta,Yasuhiro KoderaSeiji,Geert Hellings,Julien Ryckaert	2022	31
11	Introducing 2D-FETs in Device Scaling Roadmap using DTCO José Raúl Rendón Sáenz,Aryan Afzalian,T. Schram,Doyoung Jang,Devin Verreck,Quentin Smets,P. Schuddinck,Bilal Chehab,Surajit Sutar,Goutham Arutchelvan,Oksana Viktorovna Shurygina,Inge Asselberghs,A. Spessot,Iuliana Radu,Bertrand Parvais,Julien Ryckaert,Иванов Сергеи Вячеславович	2020	33
12	Device-, Circuit- & Block-level evaluation of CFET in a 4 track library P. Schuddinck,Odysseas Zografos,Pieter Weckx,Prachand Man Pradhan,Santonu Sarkar,Yasser Sherazi,Rogier Baert,Doyoung Jang,Dmitry Yakimets,Anshul Gupta,Bertrand Parvais,Julien Ryckaert,Diederik Verkest,A. Mocuta	2019	53
13	Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller! Julien Ryckaert,Иванов Сергеи Вячеславович,Pieter Weckx,Doyoung Jang,P. Schuddinck,Bilal Chehab,K. Bar-Yaacov,Santonu Sarkar,Cut Sarah Faradilla,Rogier Baert,Diederik Verkest	2019	65
14	The Complementary FET (CFET) for CMOS scaling beyond N3 Julien Ryckaert,P. Schuddinck,Pieter Weckx,G. Bouche,Benjamin Vincent,N. C. Lopez,Yasser Sherazi,A. Mallik,Hans Mertens,S. Demuynck,Trong Huynh-Bao,A. Veloso,Naoto Horiguchi,A. Mocuta,D. Mocuta,Juergen Boemmels	2018	147
15	Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm Pieter Weckx,Julien Ryckaert,V. Putcha,A. De Keersgieter,Juergen Boemmels,P. Schuddinck,Doyoung Jang,Dmitry Yakimets,M. Garcia Bardon,L.-Å. Ragnarsson,Prasanth Raghavan,Maks Vinšćak,A. Spessot,Diederik Verkest,A. Mocuta	2017	39
16	Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node IEEE Transactions on Electron Devices ·Doyoung Jang,Dmitry Yakimets,Geert Eneman,P. Schuddinck,M. Garcia Bardon,Praveen Raghavan,A. Spessot,Diederik Verkest,A. Mocuta	2017	208
17	Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology Dmitry Yakimets,M. Garcia Bardon,Doyoung Jang,P. Schuddinck,Yasser Sherazi,Pieter Weckx,Kenichi Miyaguchi,Bertrand Parvais,Prasanth Raghavan,A. Spessot,Diederik Verkest,A. Mocuta	2017	84
18	Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires M. Garcia Bardon,Yasser Sherazi,P. Schuddinck,Doyoung Jang,Dmitry Yakimets,Peter Debacker,Rogier Baert,Hans Mertens,Mustafa Badaroglu,A. Mocuta,Naoto Horiguchi,D. Mocuta,Prasanth Raghavan,Julien Ryckaert,A. Spessot,Diederik Verkest,An Steegen	2016	53
19	Vertical device architecture for 5nm and beyond: Device & circuit implications A. V-Y. Thean,Dmitry Yakimets,Trong Huynh-Bao,P. Schuddinck,Antoine Ginésy,M. Garcia Bardon,A. Sibaja-Hernandez,Ivan Ciofi,Geert Eneman,A. Veloso,Julien Ryckaert,Prasanth Raghavan,A. Mercha,A. Mocuta,Zs. Tôkei,Diederik Verkest,Piet Wambacq,K. De Meyer,Nadine Collaert	2015	40
20	DTCO at N7 and beyond: patterning and electrical compromises and opportunities Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Julien Ryckaert,Praveen Raghavan,P. Schuddinck,Trong Huynh-Bao,Arindam Mallik,Antoine Ginésy,Khotsianova Sa,Yasser Sherazi,Philippe Leray,A. Mercha,J. Bömmels,Gregory McIntyre,Kurt Ronse,Aaron Thean,Zsolt Tökei,An Steegen,Diederik Verkest	2015	26

About P. Schuddinck

P. Schuddinck is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Electronic, Optical and Magnetic Materials, having authored 55 papers that have together received 1.5k indexed citations. Recurring topics across this work include Semiconductor materials and devices (50 papers), Advancements in Semiconductor Devices and Circuit Design (47 papers), Low-power high-performance VLSI design (16 papers), Ferroelectric and Negative Capacitance Devices (16 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers), Advancements in Photolithography Techniques (3 papers), 3D IC and TSV technologies (3 papers) and Nanowire Synthesis and Applications (3 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.4k citations), Hardware and Architecture (94 citations) and Biomedical Engineering (307 citations). P. Schuddinck has collaborated with scholars based in Belgium, United States and France. Frequent co-authors include Diederik Verkest, Doyoung Jang, Dmitry Yakimets, M. Garcia Bardon, Julien Ryckaert, A. Mocuta, Pieter Weckx, Geert Eneman, A. Spessot and Praveen Raghavan. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Journal of Micro/Nanolithography MEMS and MOEMS, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Journal of the Electron Devices Society.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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