B. Prévitali

2.8k total citations
81 papers, 1.4k citations indexed

About

B. Prévitali is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Biomedical Engineering. According to data from OpenAlex, B. Prévitali has authored 81 papers receiving a total of 1.4k indexed citations (citations by other indexed papers that have themselves been cited), including 78 papers in Electrical and Electronic Engineering, 20 papers in Atomic and Molecular Physics, and Optics and 16 papers in Biomedical Engineering. Recurrent topics in B. Prévitali's work include Semiconductor materials and devices (66 papers), Advancements in Semiconductor Devices and Circuit Design (56 papers) and Integrated Circuits and Semiconductor Failure Analysis (13 papers). B. Prévitali is often cited by papers focused on Semiconductor materials and devices (66 papers), Advancements in Semiconductor Devices and Circuit Design (56 papers) and Integrated Circuits and Semiconductor Failure Analysis (13 papers). B. Prévitali collaborates with scholars based in France, Switzerland and Czechia. B. Prévitali's co-authors include S. Deleonibus, M. Vinet, C. Tabone, T. Poiroux, C. Le Royer, F. Andrieu, O. Faynot, J. Widiez, Jean‐Michel Hartmann and J. Lolivier and has published in prestigious journals such as Applied Physics Letters, Physical Review B and Applied Surface Science.

In The Last Decade

B. Prévitali

79 papers receiving 1.4k citations

Peers

Countries citing papers authored by B. Prévitali

Since Specialization

Citations

This map shows the geographic impact of B. Prévitali's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by B. Prévitali with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites B. Prévitali more than expected).

Fields of papers citing papers by B. Prévitali

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by B. Prévitali. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by B. Prévitali. The network helps show where B. Prévitali may publish in the future.

Co-authorship network of co-authors of B. Prévitali

This figure shows the co-authorship network connecting the top 25 collaborators of B. Prévitali. A scholar is included among the top collaborators of B. Prévitali based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with B. Prévitali. B. Prévitali is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	An Assessment of the Lateral Selective Etching, with HCl, of High Versus Low Ge Content SiGe Layers 2024 ·ECS Transactions ·Jean-Michel Hartmann, B. Prévitali, F. Aussenac, (unknown), (unknown), (unknown), (unknown), Sylvain Barraud	0
2	Fabrication of Low-Power RRAM for Stateful Hyperdimensional Computing 2023 ·SPIRE - Sciences Po Institutional REpository ·(unknown), Sylvain Barraud, B. Prévitali, S. Martinie, J. Lacord, Sébastien Martin, (unknown), (unknown), F. Andrieu	1
3	Optimum Functionalization of Si Nanowire FET for Electrical Detection of DNA Hybridization 2022 ·IEEE Journal of the Electron Devices Society ·(unknown), B. Prévitali, (unknown), Guillaume Nonglaton, Valérie Stambouli, Sylvain Barraud	7
4	7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing 2020 ·SPIRE - Sciences Po Institutional REpository ·Sylvain Barraud, B. Prévitali, C. Vizioz, Jean‐Michel Hartmann, J. A. Sturm, (unknown), C. Perrot, (unknown), V. Loup, (unknown), R. Kies, G. Romano, M. Cassé, Nicolas Bernier, (unknown), Adeline Grenier, F. Andrieu	71
5	Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies 2019 ·Semiconductor Science and Technology ·Sylvain Barraud, B. Prévitali, V. Lapras, R. Coquand, C. Vizioz, (unknown), M. Cassé	14
6	Stacked-Wires FETs for Advanced CMOS Scaling 2017 ·Sylvain Barraud, V. Lapras, Marie-Pierre Samson, B. Prévitali, Jean‐Michel Hartmann, N. Rambal, (unknown), (unknown), (unknown), François Triozon, Nicolas Bernier, David Cooper, (unknown)	2
7	FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration 2015 ·Solid-State Electronics ·C. Fenouillet-Béranger, B. Prévitali, P. Batude, F. Nemouchi, M. Cassé, X. Garros, L. Tosti, N. Rambal, D. Lafond, H. Dansas, L. Pasini, Laurent Brunet, Fabien Deprat, M. Grégoire, M. Mellier, M. Vinet	19
8	FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration 2014 ·C. Fenouillet-Béranger, B. Prévitali, P. Batude, F. Nemouchi, M. Cassé, X. Garros, L. Tosti, N. Rambal, D. Lafond, H. Dansas, L. Pasini, Laurent Brunet, Fabien Deprat, M. Grégoire, M. Mellier, (unknown)	23
9	Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs 2013 ·Solid-State Electronics ·B. Sklénard, P. Batude, Quentin Rafhay, Ignacio Martin‐Bragado, (unknown), B. Prévitali, B. Colombeau, (unknown), S. Cristoloveanu, P. Rivallin, C. Tavernier, T. Poiroux	1
10	Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor 2013 ·Solid-State Electronics ·Veeresh Deshpande, Sylvain Barraud, X. Jehl, R. Wacquez, M. Vinet, R. Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, B. Prévitali, P. Perreau, T. Poiroux, M. Sanquer, O. Faynot	22
11	Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities 2012 ·Veeresh Deshpande, Sylvain Barraud, X. Jehl, R. Wacquez, M. Vinet, R. Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, B. Prévitali, P. Perreau, T. Poiroux, M. Sanquer, O. Faynot	10
12	Realization of both a single electron transistor and a field effect transistor with an underlapped FDSOI MOSFET geometry 2012 ·B. Roche, B. Voisin, X. Jehl, M. Sanquer, R. Wacquez, M. Vinet, Veeresh Deshpande, B. Prévitali	1
13	Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length 2011 ·Symposium on VLSI Technology ·P. Batude, M. Vinet, Chuan Xu, B. Prévitali, C. Tabone, C. Le Royer, L. Sanchez, L. Baud, Laurent Brunet, A. Toffoli, F. Allain, D. Lafond, F. Aussenac, Ο. Thomas, T. Poiroux, O. Faynot	13
14	3D monolithic integration 2011 ·P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Prévitali, C. Tabone, Jean‐Michel Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, S. Deleonibus, O. Faynot	18
15	Ion-Ioff performance analysis of FDSOI MOSFETs with low processing temperature 2010 ·(unknown), P. Batude, (unknown), C. Le Royer, Louis Hutin, A. Pouydebasque, (unknown), B. Prévitali, M. Vinet, M. Mouis, (unknown)	1
16	Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain 2009 ·IEEE Electron Device Letters ·M. Vinet, T. Poiroux, Christophe Licitra, J. Widiez, (unknown), B. Prévitali, C. Vizioz, D. Lafond, C. Arvet, P. Besson, L. Baud, Y. Morand, M. Rivoire, F. Nemouchi, V. Carron, S. Deleonibus	10
17	Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance 2008 ·F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Prévitali, S. Deleonibus	198
18	Germanium-On-Nothing (GeON): an innovative technology for ultrathin Ge film integration 2007 ·(unknown), S. Monfray, D. Rideau, (unknown), N. Loubet, T. Skotnicki, C. Tabone, (unknown), S. Borel, (unknown), (unknown), Benjamin Vincent, B. Prévitali, L. Clavelier, Marc Bescond, G. Ghibaudo	2
19	Towards the limits of conventional MOSFETs: case of sub 30 nm NMOS devices 2004 ·Solid-State Electronics ·G. Bertrand, S. Deleonibus, B. Prévitali, G. Guégan, X. Jehl, M. Sanquer, F. Balestra	25
20	Full CMP Integration of TiN Damascene Metal Gate Devices 2000 ·(unknown), F. Ducroquet, (unknown), B. Prévitali, (unknown), (unknown), (unknown), Y. Gobil, M. Heitzmann, S. Tedesco, (unknown), S. Deleonibus	2

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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