V. Maffini-Alvaro

963 citations

20 papers · 378 indexed · h-index 12

Co-authors: Jean‐Michel Hartmann C. Vizioz Sylvain Barraud F. Aussenac R. Coquand C. Comboroure V. Delaye M. Cassé
Topics: Semiconductor materials and devices (20 papers)Advancements in Semiconductor Devices and Circuit Design (18 papers)Nanowire Synthesis and Applications (14 papers)
Cited by: Electrical and Electronic Engineering Biomedical Engineering Structural Biology
Journals: Applied Physics Letters IEEE Transactions on Electron Devices IEEE Electron Device Letters
Partner nations: France Japan United States

In The Last Decade

V. Maffini-Alvaro

20 papers receiving 365 citations

Peers

Countries citing papers authored by V. Maffini-Alvaro

Since Specialization

Citations

This map shows the geographic impact of V. Maffini-Alvaro's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Maffini-Alvaro with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Maffini-Alvaro more than expected).

Fields of papers citing papers by V. Maffini-Alvaro

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by V. Maffini-Alvaro. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Maffini-Alvaro. The network helps show where V. Maffini-Alvaro may publish in the future.

Co-authorship network of co-authors of V. Maffini-Alvaro

This figure shows the co-authorship network connecting the top 25 collaborators of V. Maffini-Alvaro. A scholar is included among the top collaborators of V. Maffini-Alvaro based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with V. Maffini-Alvaro. V. Maffini-Alvaro is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Opportunities and challenges of nanowire-based CMOS technologies 2015 ·Sylvain Barraud,M. Cassé,(unknown),P. Nguyen,Jean‐Michel Hartmann,Marie-Pierre Samson,V. Maffini-Alvaro,C. Tabone,C. Vizioz,C. Arvet,Patricia Pimenta‐Barros,(unknown),Nicolas Bernier,O. Rozeau,M.-A. Jaud,S. Martinie,(unknown),F. Allain,B. De Salvo,M. Vinet	11
2	High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique 2014 ·P. Nguyen,Sylvain Barraud,Masahiro Koyama,M. Cassé,(unknown),C. Tabone,(unknown),Jean‐Michel Hartmann,V. Maffini-Alvaro,D. Rouchon,Nicolas Bernier,D. Lafond,Marie-Pierre Samson,F. Allain,C. Vizioz,D. Delprat,Bich-Yen Nguyen,C. Mazuré,O. Faynot,M. Vinet	3
3	Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors 2014 ·IEEE Transactions on Electron Devices ·Sylvain Barraud,Jean‐Michel Hartmann,V. Maffini-Alvaro,L. Tosti,V. Delaye,D. Lafond	13
4	(Invited) Strain-Enhanced Performance of Si-Nanowire FETs 2013 ·ECS Transactions ·M. Cassé,Sylvain Barraud,R. Coquand,Masahiro Koyama,David Cooper,C. Vizioz,C. Comboroure,P. Perreau,V. Maffini-Alvaro,C. Tabone,L. Tosti,S. Barnola,V. Delaye,F. Aussenac,G. Ghibaudo,Hiroshi Iwai,G. Reimbold	4
5	Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length 2013 ·IEEE Electron Device Letters ·Sylvain Barraud,R. Coquand,Jean‐Michel Hartmann,V. Maffini-Alvaro,Marie-Pierre Samson,L. Tosti,F. Allain	14
6	Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs 2013 ·Solid-State Electronics ·Masahiro Koyama,M. Cassé,R. Coquand,Sylvain Barraud,C. Vizioz,C. Comboroure,P. Perreau,V. Maffini-Alvaro,C. Tabone,L. Tosti,S. Barnola,V. Delaye,F. Aussenac,G. Ghibaudo,Hiroshi Iwai,G. Reimbold	17
7	Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width 2013 ·Solid-State Electronics ·R. Coquand,Sylvain Barraud,M. Cassé,Paul Leroux,C. Vizioz,C. Comboroure,P. Perreau,E Ernst,Marie-Pierre Samson,V. Maffini-Alvaro,C. Tabone,S. Barnola,Daniela Munteanu,G. Ghibaudo,S. Monfray,F. Bœuf,T. Poiroux	15
8	Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm 2012 ·IEEE Electron Device Letters ·Sylvain Barraud,R. Coquand,M. Cassé,Masahiro Koyama,Jean‐Michel Hartmann,V. Maffini-Alvaro,C. Comboroure,C. Vizioz,F. Aussenac,O. Faynot,T. Poiroux	97
9	Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width 2012 ·R. Coquand,Sylvain Barraud,M. Cassé,Paul Leroux,C. Vizioz,C. Comboroure,P. Perreau,E Ernst,Marie-Pierre Samson,V. Maffini-Alvaro,C. Tabone,S. Barnola,Daniela Munteanu,G. Ghibaudo,S. Monfray,F. Bœuf,T. Poiroux	42
10	3D source/drain doping optimization in Multi-Channel MOSFET 2010 ·K. Tachi,Nathalie Vulliet,Sylvain Barraud,B. Guillaumot,V. Maffini-Alvaro,C. Vizioz,C. Arvet,Y. Campidelli,P. Gautier,Jean‐Michel Hartmann,T. Skotnicki,S. Cristoloveanu,Hiroshi Iwai,O. Faynot,T. Ernst	4
11	3D Suspended Nanowires Integration for CMOS and Beyond 2009 ·ECS Transactions ·T. Ernst,K. Tachi,(unknown),(unknown),C. Dupré,Stéphane Bécu,Nathalie Vulliet,Émilie Bernard,(unknown),V. Maffini-Alvaro,Jean‐François Damlencourt,C. Vizioz,(unknown),Caroline Bonafos,Jean‐Michel Hartmann	2
12	A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration 2009 ·(unknown),E. Nowak,K. Tachi,V. Maffini-Alvaro,C. Vizioz,C. Arvet,J. P. Colonna,Jean‐Michel Hartmann,V. Loup,L. Baud,(unknown),V. Delaye,C. Carabasse,G. Molas,G. Ghibaudo,B. De Salvo,O. Faynot,T. Ernst	9
13	Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires 2009 ·K. Tachi,M. Cassé,Doyoung Jang,C. Dupré,(unknown),Nathalie Vulliet,V. Maffini-Alvaro,C. Vizioz,C. Carabasse,V. Delaye,Jean‐Michel Hartmann,G. Ghibaudo,Hiroshi Iwai,S. Cristoloveanu,O. Faynot,T. Ernst	23
14	Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization 2008 ·ECS Transactions ·(unknown),(unknown),Stéphane Bécu,C. Dupré,V. Maffini-Alvaro,Jean‐Michel Hartmann,(unknown),C. Vizioz,F. Aussenac,C. Carabasse,V. Delaye,T. Ernst,S. Deleonibus	15
15	Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI 2008 ·Solid-State Electronics ·Émilie Bernard,T. Ernst,B. Guillaumot,Nathalie Vulliet,X. Garros,V. Maffini-Alvaro,P. Coronel,T. Skotnicki,S. Deleonibus	11
16	Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications 2008 ·ECS Transactions ·S. Barnola,C. Vizioz,Nathalie Vulliet,C. Dupré,T. Ernst,P. Gautier,C. Arvet,B. Guillaumot,Émilie Bernard,(unknown),C. Comboroure,Jean‐Michel Hartmann,S. Borel,T. Chevolleau,V. Maffini-Alvaro,Stéphane Bécu	10
17	Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack 2008 ·Émilie Bernard,T. Ernst,B. Guillaumot,Nathalie Vulliet,V. Barral,V. Maffini-Alvaro,F. Andrieu,C. Vizioz,Y. Campidelli,P. Gautier,Jean‐Michel Hartmann,R. Kies,V. Delaye,F. Aussenac,T. Poiroux,P. Coronel,A. Souifi,T. Skotnicki,S. Deleonibus	21
18	3D stacked channels: how series resistances can limit 3D devices performance 2007 ·Émilie Bernard,T. Ernst,B. Guillaumot,Nathalie Vulliet,V. Maffini-Alvaro,F. Andrieu,(unknown),P. Rivallin,C. Vizioz,Y. Campidelli,(unknown),Jean‐Michel Hartmann,S. Borel,V. Delaye,A. Pouydebasque,(unknown),P. Coronel,T. Skotnicki,S. Deleonibus	7
19	3D nanowire gate-all-around transistors: Specific integration and electrical features 2007 ·Solid-State Electronics ·C. Dupré,T. Ernst,V. Maffini-Alvaro,V. Delaye,Jean‐Michel Hartmann,S. Borel,C. Vizioz,O. Faynot,G. Ghibaudo,S. Deleonibus	23
20	Hydrogen annealing of arrays of planar and vertically stacked Si nanowires 2007 ·Applied Physics Letters ·(unknown),T. Ernst,J.-Ch. Barbé,Jean‐Michel Hartmann,V. Delaye,F. Aussenac,C. Vizioz,S. Borel,V. Maffini-Alvaro,Christian Isheden,J. Foucher	37

About V. Maffini-Alvaro

V. Maffini-Alvaro is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Infectious Diseases, having authored 20 papers that have together received 378 indexed citations. Recurring topics across this work include Semiconductor materials and devices (20 papers), Advancements in Semiconductor Devices and Circuit Design (18 papers) and Nanowire Synthesis and Applications (14 papers). The work is most often cited by research in Electrical and Electronic Engineering (367 citations), Biomedical Engineering (161 citations) and Structural Biology (5 citations). V. Maffini-Alvaro has collaborated with scholars based in France, Japan and United States. Frequent co-authors include Jean‐Michel Hartmann, C. Vizioz, Sylvain Barraud, F. Aussenac, R. Coquand, C. Comboroure, V. Delaye, M. Cassé, T. Poiroux and T. Ernst. Their work appears in journals such as Applied Physics Letters, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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