C. Radens

1.1k citations

23 papers · 582 indexed · h-index 8

Hardware and Architecture top 5%
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices 18
- Advancements in Semiconductor Devices and Circuit Design 16
- Ferroelectric and Negative Capacitance Devices 6
- Low-power high-performance VLSI design 6
- Integrated Circuits and Semiconductor Failure Analysis 4
- Photonic and Optical Devices 3
- Advancements in Photolithography Techniques 2
Computer Networks and Communications top 10%
Atomic and Molecular Physics, and Optics
- Semiconductor Quantum Structures and Devices 2
Surfaces, Coatings and Films

Co-authors: Stephen Kosonocky A.J. Bhavnagarwala Kevin StawiaszY. LiJ. DeBrosse R.H. Dennard R. Divakaruni G. Bronner
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computer Networks and Communications
Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (3 papers)IEEE Journal of Solid-State Circuits (3 papers)IEEE Journal of Quantum Electronics (2 papers)
Partner nations: United States Lebanon Germany

In The Last Decade

C. Radens

20 papers receiving 549 citations

Peers

Countries citing papers authored by C. Radens

Since Specialization

Citations

This map shows the geographic impact of C. Radens's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Radens with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Radens more than expected).

Fields of papers citing papers by C. Radens

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Radens. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Radens. The network helps show where C. Radens may publish in the future.

Co-authorship network

The 25 scholars most cited alongside C. Radens, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with C. Radens Line = papers co-authored together C. Radens links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets Indira Seshadri,Minda Le,Prateek Hundekar,Pauline Georgiades,Jingyun Zhang,Eric R. Miller,Andrew Greene,Julien Frougier,Shengm Zhong,Tao Li,Amanda Alvariz Lopes,Xiaocong Fu,C. Radens,Stuart Sieg,Veeraraghavan Basker,Nelson Felix,Chris A. Mack	2021	3
2	A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s (Conference Presentation) Indira Seshadri,JimmyLolu,Stuart Sieg,Tao Li,K.-Y. Lee,Eric R. Miller,Andrei Volodichev,Andrew Greene,C. Radens,Jingyun Zhang,Yann Mignot,P. Montanini,Pauline Georgiades,Veeraraghavan Basker,Nelson Felix	2020	1
3	An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·R. Mann,Wilfrida A Ogonda,Philipp Steinert,Qun Gao,Bunga Anisa Abu Bakar,C. Radens,Zbyněk Tomiška,他谷康,J.M. Higman,Rick Carter	2019	0
4	A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Rajiv Joshi,Sudesh Saroop,Rouwaida Kanj,Yang Liu,Н. Ю. Стожко,C. Radens,Yue Tan,Karthik Yogendra	2015	4
5	Fully-depleted planar technologies and static RAM Terence B. Hook,Kangguo Cheng,B. Doris,A. Khakifirooz,J. Anan,S. Ponoth,C. Radens,M. Vinet	2013	1
6	A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements Harold Pilo,Igor Arsovski,David Gallus,G. Braceras,Ndidiamka Patients Ukeje,R. Houle,博見畑野,Dominic Nelson,G Habib,Liang-Yü Chen,潘善新,C. Radens	2011	35
7	A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements IEEE Journal of Solid-State Circuits ·Harold Pilo,Igor Arsovski,David Gallus,G. Braceras,Ndidiamka Patients Ukeje,R. Houle,博見畑野,C. Radens,G Habib	2011	68
8	A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing IEEE Journal of Solid-State Circuits ·A.J. Bhavnagarwala,Stephen Kosonocky,C. Radens,Y.H. Chan,Kevin Stawiasz,Uma Srinivasan,Steven P. Kowalczyk,Matthew M. Ziegler	2008	72
9	Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells A.J. Bhavnagarwala,Stephen Kosonocky,C. Radens,Kevin Stawiasz,R. Mann,Roberta Machado de Souza,Ken K. Chin	2006	126
10	Technologies for scaling vertical transistor DRAM cells to 70 nm R. Divakaruni,C. Radens,Michael Belyansky,M. Chudzik,J. Eysséric,Sudesh Saroop,D. Chidambarrao,M. Weybright,Abdelilah Fahde,Laertis Economikos,Ted Otis,J. Strane,D. Dobuzinsky,N.L. Edleman,Feng Gao,Y. Li,R. Jammy,E.F. Crabbé,G. Bronner	2004	3
11	Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology Prandoni,Melissa Anne Love,Davide Brocchi,Laertis Economikos,C. Parks,C. Radens,Amelia Putri Eka Yusiana,笠井昭吾	2003	1
12	Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides Ernest Y. Wu,R.‐P. Vollertsen,Christelle Charlebois,A. Strong,C. Radens	2003	2
13	Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applications Ernest Y. Wu,P G Gonzales Ormeño,R.‐P. Vollertsen,Hua Shen,Seulgi Hong,C. Radens,A. Strong	2002	8
14	A lithographically-friendly 6F/sup 2/ DRAM cell Zhenhua Wei,J. Mandelman,Alan C. Thomas,C. Radens,G. Kunkel	2002	0
15	Challenges and future directions for the scaling of dynamic random-access memory (DRAM) IBM Journal of Research and Development ·J. Mandelman,R.H. Dennard,G. Bronner,J. DeBrosse,R. Divakaruni,Y. Li,C. Radens	2002	183
16	A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs IEEE Journal of Solid-State Circuits ·H. Hoenigschmid,Alexander Frey,J. DeBrosse,T. Kirihata,Georg Mueller,RP Mann,(unknown),Txabi Arnal,YUKIO IMANISHI,David R. Hanson,Ibrahim Addai,Bing Ji,Jamie M. Knapil Infantolino,P.H.Th.J. Slee,C. Radens,Sinan A. Neftci,Hanna Venesvirta,Yuichi Kamiyoshi,Fritz Larsen,W. Weber,M.R. Wordeman	2000	3
17	Slotted vias for dual damascene interconnects in 1 Gb DRAMs R. Schnabel,G. Bronner,L. A. Clevenger,D. Dobuzinsky,G. Costrini,R. G. Filippi,Jeff Gambino,達雄谷,Wilford J. Ratzan,Chang-Hsien Lin,K.P. Müller,Georg Mueller,I.‐W. Ting,C. Radens,Serge Weber,Pierre Bertin	1999	2
18	Length minimization in integrated optical circuits incorporating directional couplers and curved sections Journal of Lightwave Technology ·В И Шариков,C. Radens,J. T. Boyd	1990	6
19	Effect of Stress on field Confinement in Channel Waveguides formed by Defining Si₃N₄ Ridges on GaALAS Multilayer Structures MRS Proceedings ·C. Radens,P.T. Branagan,Howard E. Jackson,J. T. Boyd,R. D. Burnham	1989	1
20	Raman microprobe analysis of strain induced by patterned dielectric films of GaAlAs structures IEEE Journal of Quantum Electronics ·C. Radens,P.T. Branagan,Howard E. Jackson,J. T. Boyd,R. D. Burnham	1989	8

About C. Radens

C. Radens is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Surfaces, Coatings and Films, having authored 23 papers that have together received 582 indexed citations. Recurring topics across this work include Semiconductor materials and devices (18 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Ferroelectric and Negative Capacitance Devices (6 papers), Low-power high-performance VLSI design (6 papers), Integrated Circuits and Semiconductor Failure Analysis (4 papers), Photonic and Optical Devices (3 papers), Advancements in Photolithography Techniques (2 papers) and Semiconductor Quantum Structures and Devices (2 papers). The work is most often cited by research in Hardware and Architecture (127 citations), Electrical and Electronic Engineering (532 citations) and Computer Networks and Communications (69 citations). C. Radens has collaborated with scholars based in United States, Lebanon and Germany. Frequent co-authors include Stephen Kosonocky, A.J. Bhavnagarwala, Kevin Stawiasz, Y. Li, J. DeBrosse, R.H. Dennard, R. Divakaruni, G. Bronner, J. Mandelman and Ken K. Chin. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Journal of Solid-State Circuits, IEEE Journal of Quantum Electronics, IEEE Electron Device Letters and Journal of Lightwave Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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