A.J. Bhavnagarwala

1.4k citations

24 papers · 1.1k indexed · 1 hit paper · h-index 11

Co-authors: J.D. Meindl Xinghai Tang Stephen Kosonocky Kevin Stawiasz C. Radens S. P. Kowalczyk Ken K. Chin Uma Srinivasan
Topics: Low-power high-performance VLSI design (19 papers)Advancements in Semiconductor Devices and Circuit Design (19 papers)Semiconductor materials and devices (13 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Statistics, Probability and Uncertainty
Journals: IEEE Journal of Solid-State Circuits IEEE Electron Device Letters IBM Journal of Research and Development
Partner nations: United States Spain Japan

In The Last Decade

A.J. Bhavnagarwala

23 papers receiving 994 citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

2001 537 citations A.J. Bhavnagarwala, Xinghai Tang et al. IEEE Journal of Solid-State Circuits profile →

Peers

Countries citing papers authored by A.J. Bhavnagarwala

Since Specialization

Citations

This map shows the geographic impact of A.J. Bhavnagarwala's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A.J. Bhavnagarwala with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A.J. Bhavnagarwala more than expected).

Fields of papers citing papers by A.J. Bhavnagarwala

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A.J. Bhavnagarwala. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A.J. Bhavnagarwala. The network helps show where A.J. Bhavnagarwala may publish in the future.

Co-authorship network of co-authors of A.J. Bhavnagarwala

This figure shows the co-authorship network connecting the top 25 collaborators of A.J. Bhavnagarwala. A scholar is included among the top collaborators of A.J. Bhavnagarwala based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with A.J. Bhavnagarwala. A.J. Bhavnagarwala is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	The semiconductor industry in 2025. 2010 ·A.J. Bhavnagarwala,Shekhar Borkar,Takayasu Sakurai,S. Narendra	1
2	EP2: The semiconductor industry in 2025 2010 ·A.J. Bhavnagarwala,Shekhar Borkar,Takayasu Sakurai,S. Narendra	1
3	A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing 2008 ·IEEE Journal of Solid-State Circuits ·A.J. Bhavnagarwala,Stephen Kosonocky,C. Radens,Y.H. Chan,Kevin Stawiasz,Uma Srinivasan,Steven P. Kowalczyk,Matthew M. Ziegler	72
4	A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing 2007 ·A.J. Bhavnagarwala,Stephen Kosonocky,Y.H. Chan,Kevin Stawiasz,Uma Srinivasan,S. P. Kowalczyk,(unknown)	28
5	Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells 2006 ·A.J. Bhavnagarwala,Stephen Kosonocky,C. Radens,Kevin Stawiasz,R. Mann,(unknown),Ken K. Chin	126
6	Scalability options for future SRAM memories 2006 ·Stephen Kosonocky,A.J. Bhavnagarwala,Leland Chang	2
7	A pico-joule class, 1 GHz, 32 KByte×64 b DSP SRAM with self reverse bias 2004 ·A.J. Bhavnagarwala,Stephen Kosonocky,M. Immediato,D.R. Knebel,(unknown)	28
8	Low-power circuits and technology for wireless digital systems 2003 ·IBM Journal of Research and Development ·Stephen Kosonocky,A.J. Bhavnagarwala,Ken K. Chin,George Gristede,(unknown),Wei Hwang,M. B. Ketchen,Seyoung Kim,D.R. Knebel,(unknown),Victor Zyuban	22
9	Generic models for interconnect delay across arbitrary wire-tree networks 2002 ·A.J. Bhavnagarwala,(unknown),J.D. Meindl	5
10	Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010 2002 ·A.J. Bhavnagarwala,(unknown),J.D. Meindl	1
11	Interconnect-centric array architectures for minimum SRAM access time 2002 ·A.J. Bhavnagarwala,Stephen Kosonocky,J.D. Meindl	4
12	Analysis of the effect of the gate oxide breakdown on SRAM stability 2002 ·Microelectronics Reliability ·R. Rodrı́guez,J. H. Stathis,B.P. Linder,S. P. Kowalczyk,C.T. Chuang,(unknown),(unknown),K. Bernstein,A.J. Bhavnagarwala,S. Lombardo	3
13	Optimal circuit design for low power CMOS GSI 2002 ·A.J. Bhavnagarwala,Vivek De,(unknown),J.D. Meindl	1
14	The impact of intrinsic device fluctuations on CMOS SRAM cell stabilitybreakdown → 2001 ·IEEE Journal of Solid-State Circuits ·A.J. Bhavnagarwala,Xinghai Tang,J.D. Meindl	537
15	Source-pulsed dynamic-threshold CMOS SRAMs for fast, portable applications 2000 ·European Solid-State Circuits Conference ·A.J. Bhavnagarwala,Ajay Kapoor,J.D. Meindl	4
16	Fluctuation Limits on Scaling of CMOS SRAMs 2000 ·A.J. Bhavnagarwala,Ajay Kapoor,J.D. Meindl	2
17	CMOS system-on-a-chip voltage scaling beyond 50nm 2000 ·A.J. Bhavnagarwala,(unknown),A. K. Kapoor,J.D. Meindl	3
18	A minimum total power methodology for projecting limits on CMOS GSI 2000 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·A.J. Bhavnagarwala,(unknown),Keith Bowman,J.D. Meindl	48
19	Minimum supply voltage for bulk Si CMOS GSI 1998 ·A.J. Bhavnagarwala,(unknown),J.D. Meindl	7
20	Circuit techniques for low-power CMOS GSI 1996 ·A.J. Bhavnagarwala,Vivek De,(unknown),J.D. Meindl	10

About A.J. Bhavnagarwala

A.J. Bhavnagarwala is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering, having authored 24 papers that have together received 1.1k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (19 papers), Advancements in Semiconductor Devices and Circuit Design (19 papers) and Semiconductor materials and devices (13 papers). The work is most often cited by research in Hardware and Architecture (276 citations), Electrical and Electronic Engineering (1.1k citations) and Statistics, Probability and Uncertainty (13 citations). A.J. Bhavnagarwala has collaborated with scholars based in United States, Spain and Japan. Frequent co-authors include J.D. Meindl, Xinghai Tang, Stephen Kosonocky, Kevin Stawiasz, C. Radens, S. P. Kowalczyk, Ken K. Chin, Uma Srinivasan, R. Mann and Y.H. Chan. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Electron Device Letters and IBM Journal of Research and Development.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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