Stephen Kosonocky

1.9k citations

56 papers · 1.3k indexed · h-index 21

Impact in

Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 5%
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- VLSI and FPGA Design Techniques

Papers in

Hardware and Architecture 24
- Parallel Computing and Optimization Techniques 14
- Embedded Systems Design Techniques 8
Electrical and Electronic Engineering 46
- Low-power high-performance VLSI design 40
- Advancements in Semiconductor Devices and Circuit Design 19
- Semiconductor materials and devices 14
- VLSI and FPGA Design Techniques 6

Co-authors: D.R. Knebel Suhwan Kim Kevin Stawiasz Anantha P. Chandrakasan A.J. Bhavnagarwala M. Immediato C. Radens R. Mann
Journals: IEEE Journal of Solid-State Circuits (5 papers)IEEE Transactions on Electron Devices (2 papers)IBM Journal of Research and Development (1 paper)Integration (1 paper)Proceedings - ACM IEEE Design Automation Conference (1 paper)
Partner nations: United States Canada South Korea

In The Last Decade

Stephen Kosonocky

53 papers receiving 1.2k citations

Peers

Countries citing papers authored by Stephen Kosonocky

Since Specialization

Citations

This map shows the geographic impact of Stephen Kosonocky's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Stephen Kosonocky with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Stephen Kosonocky more than expected).

Fields of papers citing papers by Stephen Kosonocky

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Stephen Kosonocky. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Stephen Kosonocky. The network helps show where Stephen Kosonocky may publish in the future.

Co-authors

The 25 scholars most cited alongside Stephen Kosonocky, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Stephen Kosonocky Line = papers co-authored together Stephen Kosonocky links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUs Howard M. Rosner, Gowtham Bingi, Kaushik Mazumdar, Bradford M. Beckmann, Stephen Kosonocky	2023	4
2	Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU Masaaki Ikawa, Alexander Vyacheslavovich, Zachary Francis, 咲子谷, G.P. Silva, Stephen Kosonocky, Samuel Naffziger	2016	7
3	Power/performance optimization of many-core processor SoCs TU/e Research Portal ·Stephen Kosonocky, Vladimir Stojanović, Kees van Berkel, Youjie Zeng, Jin Biaoren, Joshua Friedrich	2012	1
4	A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs Kyle Craig, Yousef Shakhsheer, Sudhanshu Khanna, O Sartor, John Lach, Benton H. Calhoun, Stephen Kosonocky	2012	2
5	Designing in scaled technologies: 32 nm and beyond Stephen Kosonocky, Tom Burd, José Micael Delgado Barbosa, AJ Mellor, L Mouton	2012	7
6	Special Issue on Device Technologies and Circuit Techniques for Power Management IEEE Transactions on Electron Devices ·J.J. Welser, Stephen Kosonocky, Tsu‐Jae King Liu, Takayasu Sakurai, R. Thewes, Bin Zhao	2008	5
7	A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing IEEE Journal of Solid-State Circuits ·A.J. Bhavnagarwala, Stephen Kosonocky, C. Radens, Y.H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler	2008	72
8	Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells A.J. Bhavnagarwala, Stephen Kosonocky, C. Radens, Kevin Stawiasz, R. Mann, Roberta Machado de Souza, Ken K. Chin	2006	126
9	Scalability options for future SRAM memories Stephen Kosonocky, A.J. Bhavnagarwala, Leland Chang	2006	2
10	Special topic evening session - SE inductance: implications and solutions for high-speed digital circuits 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·William J. Bowhill, Anantha P. Chandrakasan, Stephen Kosonocky	2005	1
11	Experimental measurement of a novel power gating structure with intermediate power saving mode Suhwan Kim, Stephen Kosonocky, D.R. Knebel, Kevin Stawiasz	2004	57
12	Supply voltage strategies for minimizing the power of CMOS processors Jin Cai, Yuan Taur, S. A. Orudjeva, D.J. Frank, Stephen Kosonocky, R.H. Dennard	2003	11
13	Optimal supply and threshold scaling for subthreshold CMOS circuits Sue Lemme, Anantha P. Chandrakasan, Stephen Kosonocky	2003	139
14	Understanding and minimizing ground bounce during mode transition of power gating structures Suhwan Kim, Stephen Kosonocky, D.R. Knebel	2003	135
15	Designing a testable system on a chip Stephen Kosonocky, A. A. Bright, Michael Volpe, R.A. Haring, S. P. Klepner, Sameh Asaad, Robert Aguilera, Анна Олеговна Разумовская, David F. Heidel, M. Immediato, Slavoljub Popović, А Фишеръ, W. Leiner, Adrienne M. Williams, Kevin Stawiasz	2002	1
16	Neural tree network/vector quantization probability estimators for speaker recognition Kevin Farrell, Stephen Kosonocky, Richard J. Mammone	2002	7
17	Low power integrated scan-retention mechanism Victor Zyuban, Stephen Kosonocky	2002	35
18	An eight-issue tree-VLIW processor for dynamic binary translation Kemal Ebci̇oğlu, Jason E. Fritts, Stephen Kosonocky, Michael Gschwind, Erik Altman, David Buckeridge, Sarah VanZoeren	2002	9
19	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design Thomas C. Dillingham, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen Kosonocky, (unknown)	2001	6
20	BOA: Targeting Multi-Gigahertz with Binary Translation S. Sathaye, Sofya Suslova, (unknown), Stephen Kosonocky, Michael Gschwind, Jason E. Fritts, A. A. Bright, Erik Altman, 公之高梨	1999	20

About Stephen Kosonocky

Stephen Kosonocky is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Software and Biomedical Engineering, having authored 56 papers that have together received 1.3k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (40 papers), Advancements in Semiconductor Devices and Circuit Design (19 papers), Parallel Computing and Optimization Techniques (14 papers), Semiconductor materials and devices (14 papers), Embedded Systems Design Techniques (8 papers), Analog and Mixed-Signal Circuit Design (8 papers), Interconnection Networks and Systems (7 papers) and VLSI and FPGA Design Techniques (6 papers). The work is most often cited by research in Hardware and Architecture (429 citations), Electrical and Electronic Engineering (1.2k citations), Computer Networks and Communications (164 citations), Biomedical Engineering (231 citations) and Software (9 citations). Stephen Kosonocky has collaborated with scholars based in United States, Canada and South Korea. Frequent co-authors include D.R. Knebel, Suhwan Kim, Kevin Stawiasz, Anantha P. Chandrakasan, A.J. Bhavnagarwala, M. Immediato, C. Radens, R. Mann, Victor Zyuban and Ken K. Chin. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices, IBM Journal of Research and Development, Integration and Proceedings - ACM IEEE Design Automation Conference.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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