G. Braceras

516 total citations
14 papers, 382 citations indexed

About

G. Braceras is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, G. Braceras has authored 14 papers receiving a total of 382 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in G. Braceras's work include Low-power high-performance VLSI design (12 papers), Advancements in Semiconductor Devices and Circuit Design (10 papers) and Semiconductor materials and devices (8 papers). G. Braceras is often cited by papers focused on Low-power high-performance VLSI design (12 papers), Advancements in Semiconductor Devices and Circuit Design (10 papers) and Semiconductor materials and devices (8 papers). G. Braceras collaborates with scholars based in United States and Spain. G. Braceras's co-authors include Harold Pilo, M. Miller, R. Houle, Igor Arsovski, C. Radens, Steven M. Burns, Junling Wang, Satyanand Nalam, Benton H. Calhoun and R. Mann and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and Solid-State Electronics.

In The Last Decade

G. Braceras

14 papers receiving 363 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
G. Braceras United States 8 375 84 15 9 6 14 382
P.R. O'Brien United States 5 204 0.5× 113 1.3× 24 1.6× 7 0.8× 6 1.0× 8 214
Harold Pilo United States 10 417 1.1× 108 1.3× 18 1.2× 10 1.1× 15 2.5× 19 428
Ajay N. Bhoj United States 11 306 0.8× 89 1.1× 16 1.1× 8 0.9× 16 2.7× 17 314
Y. Yamagami Japan 9 350 0.9× 93 1.1× 14 0.9× 4 0.4× 13 2.2× 17 353
Satyanand Nalam United States 12 435 1.2× 114 1.4× 12 0.8× 5 0.6× 15 2.5× 17 449
E. Grossar Belgium 4 405 1.1× 115 1.4× 8 0.5× 10 1.1× 13 2.2× 8 409
Yoshihiro Shinozaki Japan 5 343 0.9× 78 0.9× 18 1.2× 3 0.3× 9 1.5× 8 349
Robert Wong United States 5 245 0.7× 42 0.5× 10 0.7× 3 0.3× 5 0.8× 13 253
R. Houle United States 8 272 0.7× 77 0.9× 14 0.9× 7 0.8× 21 3.5× 14 286
R. Mahnkopf Germany 7 284 0.8× 65 0.8× 37 2.5× 3 0.3× 5 0.8× 17 290

Countries citing papers authored by G. Braceras

Since Specialization
Citations

This map shows the geographic impact of G. Braceras's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by G. Braceras with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites G. Braceras more than expected).

Fields of papers citing papers by G. Braceras

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by G. Braceras. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by G. Braceras. The network helps show where G. Braceras may publish in the future.

Co-authorship network of co-authors of G. Braceras

This figure shows the co-authorship network connecting the top 25 collaborators of G. Braceras. A scholar is included among the top collaborators of G. Braceras based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with G. Braceras. G. Braceras is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

14 of 14 papers shown
1.
Pilo, Harold, Igor Arsovski, G. Braceras, et al.. (2011). A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. 254–256. 35 indexed citations
2.
Pilo, Harold, et al.. (2011). A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE Journal of Solid-State Circuits. 47(1). 97–106. 68 indexed citations
3.
Mann, R., Junling Wang, Satyanand Nalam, et al.. (2010). Impact of circuit assist methods on margin and performance in 6T SRAM. Solid-State Electronics. 54(11). 1398–1407. 34 indexed citations
4.
Pilo, Harold, et al.. (2009). An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. IEEE Journal of Solid-State Circuits. 44(1). 155–162. 7 indexed citations
5.
Wu, Ernest Y., G. Braceras, C. Mark Johnson, et al.. (2009). A viable and comprehensive TDDB assessment methodology for investigation of SRAM V<inf>min</inf> failure. 1–4. 6 indexed citations
6.
7.
Pilo, Harold, et al.. (2007). An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. IEEE Journal of Solid-State Circuits. 42(4). 813–819. 100 indexed citations
8.
9.
Pilo, Harold, et al.. (2004). A 0.9ns random cycle 36Mb network SRAM with 33mW standby power. 284–287. 10 indexed citations
10.
Braceras, G., et al.. (2003). A 940 MHz data rate 8 Mb CMOS SRAM. 198–199. 3 indexed citations
11.
Braceras, G., et al.. (2002). A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 μm CMOS process. 404–405,. 4 indexed citations
12.
Braceras, G., et al.. (2002). A 200 MHz internal/66 MHz external 64 kB embedded virtual three-port cache SRAM. 262–263. 1 indexed citations
13.
Mukherjee, Tamal, et al.. (1990). An on-chip 72 K pseudo two-port cache memory subsystem. 113–114. 2 indexed citations
14.
Braceras, G., Robert Goodwin, T. Maffitt, et al.. (1987). A 256K SRAM with on-chip power supply conversion. 252–253. 7 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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