Harold Pilo

564 total citations
19 papers, 428 citations indexed

About

Harold Pilo is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Harold Pilo has authored 19 papers receiving a total of 428 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in Harold Pilo's work include Low-power high-performance VLSI design (12 papers), Semiconductor materials and devices (12 papers) and Advancements in Semiconductor Devices and Circuit Design (10 papers). Harold Pilo is often cited by papers focused on Low-power high-performance VLSI design (12 papers), Semiconductor materials and devices (12 papers) and Advancements in Semiconductor Devices and Circuit Design (10 papers). Harold Pilo collaborates with scholars based in United States, Switzerland and India. Harold Pilo's co-authors include G. Braceras, R. Houle, Igor Arsovski, Steven M. Burns, M. Miller, C. Radens, Junling Wang, Satyanand Nalam, Benton H. Calhoun and R. Mann and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and Solid-State Electronics.

In The Last Decade

Harold Pilo

17 papers receiving 406 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Harold Pilo United States 10 417 108 18 15 10 19 428
Ajay N. Bhoj United States 11 306 0.7× 89 0.8× 16 0.9× 16 1.1× 8 0.8× 17 314
Ku He United States 9 323 0.8× 82 0.8× 30 1.7× 15 1.0× 21 2.1× 14 335
G. Braceras United States 8 375 0.9× 84 0.8× 15 0.8× 6 0.4× 9 0.9× 14 382
D. Overhauser United States 10 289 0.7× 119 1.1× 28 1.6× 7 0.5× 9 0.9× 20 304
Davide Pandini Italy 11 296 0.7× 194 1.8× 17 0.9× 37 2.5× 7 0.7× 37 312
Masaki Hashizume Japan 8 215 0.5× 158 1.5× 14 0.8× 12 0.8× 8 0.8× 100 236
R. Houle United States 8 272 0.7× 77 0.7× 14 0.8× 21 1.4× 7 0.7× 14 286
Satyanand Nalam United States 12 435 1.0× 114 1.1× 12 0.7× 15 1.0× 5 0.5× 17 449
A.U. Diril United States 10 292 0.7× 191 1.8× 16 0.9× 20 1.3× 4 0.4× 16 298
Y.S. Dhillon United States 10 283 0.7× 186 1.7× 16 0.9× 20 1.3× 4 0.4× 14 289

Countries citing papers authored by Harold Pilo

Since Specialization
Citations

This map shows the geographic impact of Harold Pilo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Harold Pilo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Harold Pilo more than expected).

Fields of papers citing papers by Harold Pilo

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Harold Pilo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Harold Pilo. The network helps show where Harold Pilo may publish in the future.

Co-authorship network of co-authors of Harold Pilo

This figure shows the co-authorship network connecting the top 25 collaborators of Harold Pilo. A scholar is included among the top collaborators of Harold Pilo based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Harold Pilo. Harold Pilo is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

19 of 19 papers shown
1.
Pilo, Harold, et al.. (2025). A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. 498–500.
2.
3.
Arsovski, Igor, et al.. (2013). Memory design considerations for high-performance networking SoCs. 286–289. 2 indexed citations
4.
5.
Pilo, Harold, Igor Arsovski, G. Braceras, et al.. (2011). A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. 254–256. 35 indexed citations
6.
Pilo, Harold, et al.. (2011). A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE Journal of Solid-State Circuits. 47(1). 97–106. 68 indexed citations
7.
Mann, R., Junling Wang, Satyanand Nalam, et al.. (2010). Impact of circuit assist methods on margin and performance in 6T SRAM. Solid-State Electronics. 54(11). 1398–1407. 34 indexed citations
8.
Pilo, Harold & Guomin Zhang. (2010). Session 19 overview: High-performance embedded memory. 340–341. 1 indexed citations
9.
Pilo, Harold, et al.. (2009). An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. IEEE Journal of Solid-State Circuits. 44(1). 155–162. 7 indexed citations
10.
11.
Pilo, Harold, et al.. (2007). An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. IEEE Journal of Solid-State Circuits. 42(4). 813–819. 100 indexed citations
12.
Pilo, Harold, et al.. (2007). A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. 21–24. 6 indexed citations
13.
14.
Pilo, Harold, et al.. (2004). A 0.9ns random cycle 36Mb network SRAM with 33mW standby power. 284–287. 10 indexed citations
15.
Pilo, Harold, et al.. (2003). A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE Journal of Solid-State Circuits. 38(11). 1974–1980. 14 indexed citations
16.
Pilo, Harold, et al.. (2002). Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. 436–443. 2 indexed citations
17.
Pilo, Harold, et al.. (2002). Bitline contacts in high density SRAMs: design for testability and stressability. 776–782. 4 indexed citations
18.
Pilo, Harold, et al.. (2002). A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 μm CMOS process. 148–149,. 5 indexed citations
19.
Pilo, Harold, et al.. (2000). An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. IEEE Journal of Solid-State Circuits. 35(11). 1641–1647. 11 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Breakdown of academic impact, for papers by Ajay N. Bhoj Breakdown of academic impact, for papers by Ku He Breakdown of academic impact, for papers by G. Braceras Breakdown of academic impact, for papers by D. Overhauser Breakdown of academic impact, for papers by Davide Pandini Breakdown of academic impact, for papers by Masaki Hashizume Breakdown of academic impact, for papers by R. Houle Breakdown of academic impact, for papers by Satyanand Nalam Breakdown of academic impact, for papers by A.U. Diril Breakdown of academic impact, for papers by Y.S. Dhillon
Rankless by CCL
2026