Yann Civale

655 total citations
42 papers, 556 citations indexed

About

Yann Civale is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Electronic, Optical and Magnetic Materials. According to data from OpenAlex, Yann Civale has authored 42 papers receiving a total of 556 indexed citations (citations by other indexed papers that have themselves been cited), including 42 papers in Electrical and Electronic Engineering, 11 papers in Biomedical Engineering and 8 papers in Electronic, Optical and Magnetic Materials. Recurrent topics in Yann Civale's work include 3D IC and TSV technologies (30 papers), Electronic Packaging and Soldering Technologies (18 papers) and Semiconductor materials and devices (14 papers). Yann Civale is often cited by papers focused on 3D IC and TSV technologies (30 papers), Electronic Packaging and Soldering Technologies (18 papers) and Semiconductor materials and devices (14 papers). Yann Civale collaborates with scholars based in Belgium, Netherlands and Japan. Yann Civale's co-authors include Eric Beyne, Harold Philipsen, Philippe Soussan, Lis K. Nanver, Silvia Armini, Bart Swinnen, A. Redolfi, Gerald Beyer, Deniz Sabuncuoglu Tezcan and Kristof Croes and has published in prestigious journals such as Journal of The Electrochemical Society, Electrochimica Acta and IEEE Electron Device Letters.

In The Last Decade

Yann Civale

40 papers receiving 539 citations

Peers

Countries citing papers authored by Yann Civale

Since Specialization

Citations

This map shows the geographic impact of Yann Civale's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yann Civale with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yann Civale more than expected).

Fields of papers citing papers by Yann Civale

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yann Civale. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yann Civale. The network helps show where Yann Civale may publish in the future.

Co-authorship network of co-authors of Yann Civale

This figure shows the co-authorship network connecting the top 25 collaborators of Yann Civale. A scholar is included among the top collaborators of Yann Civale based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yann Civale. Yann Civale is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance 2013 ·Yann Civale, Stefaan Van Huylenbroeck, A. Redolfi, Wei Guo, (unknown), Patrick Jaenen, Antonio Manna, Gerald Beyer, Bart Swinnen, Eric Beyne	10
2	Interposer technology for high band width interconnect applications 2013 ·(unknown), Antonio Manna, Joeri De Vos, (unknown), (unknown), Yann Civale, Gerald Beyer, Eric Beyne	22
3	High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias 2013 ·Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) ·Alain Phommahaxay, Ingrid De Wolf, (unknown), Sebastian Brand, (unknown), Harold Philipsen, Yann Civale, K. Vandersmissen, Sandip Halder, Gerald Beyer, Bart Swinnen, Andy Miller, Eric Beyne	14
4	ESH Friendly Solvent for Stripping Positive and Negative Photoresists in 3D-Wafer Level Packaging and 3D-Stacked IC Applications 2012 ·Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena ·Samuel Suhard, Martine Claes, Yann Civale, (unknown), Deniz Sabuncuoglu Tezcan, Youssef Travaly	1
5	Highly-conformal plasma-enhanced atomic-layer deposition silicon dioxide liner for high aspect-ratio through-silicon via 3D interconnections 2012 ·Yann Civale, A. Redolfi, Dimitrios Velenis, N. Heylen, (unknown), (unknown), (unknown), Bart Swinnen, Gerald Beyer, Eric Beyne	14
6	Electrical characterization method to study barrier integrity in 3D through-silicon vias 2012 ·(unknown), Dimitrios Velenis, T. Kauerauf, Michele Stucchi, Yann Civale, A. Redolfi, Kristof Croes	24
7	Cost comparison between 3D and 2.5D integration 2012 ·Dimitrios Velenis, (unknown), Yann Civale, Erik Jan Marinissen, Gerald Beyer, Eric Beyne	6
8	Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects 2012 ·Yann Civale, Silvia Armini, Harold Philipsen, A. Redolfi, Dimitrios Velenis, Kristof Croes, N. Heylen, (unknown), K. Vandersmissen, Gerald Beyer, Bart Swinnen, Eric Beyne	28
9	Novel seed layer formation using direct electroless copper deposition on ALD-Ru layer for high aspect ratio TSV 2012 ·Fumihiro Inoue, Harold Philipsen, Aleksandar Radisic, Silvia Armini, Yann Civale, (unknown), Shoso Shingubara	5
10	Reliability concerns in copper TSV's: Methods and results 2012 ·Kristof Croes, Vladimir Cherman, Yunlong Li, Larry Zhao, Y. Barbarin, Joke De Messemaeker, Yann Civale, Dimitrios Velenis, Michele Stucchi, T. Kauerauf, A. Redolfi, Biljana Dimčić, (unknown), Geert Van der Plas, Ingrid De Wolf, Gerald Beyer, Bart Swinnen, Zsolt Tökei, Eric Beyne	10
11	3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias 2011 ·IEEE Transactions on Components Packaging and Manufacturing Technology ·Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen, (unknown), Patrick Jaenen, Youssef Travaly, Philippe Soussan, Bart Swinnen, Eric Beyne	42
12	Via Last using Polymer Liners and their Reliability 2010 ·Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ·Deniz Sabuncuoglu Tezcan, (unknown), Yann Civale, Philippe Soussan, Eric Beyne	3
13	A novel concept for ultra-low capacitance via-last TSV 2010 ·Yann Civale, Mario González, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne	13
14	Al-mediated Solid-Phase Epitaxy of Silicon-On-Insulator 2010 ·MRS Proceedings ·(unknown), Yann Civale, Lis K. Nanver, (unknown), Vladimir Jovanović	3
15	Seedless Copper Electrochemical Deposition on PVD Resistive Substrates as a Replacement/Enhancement for PVD Cu Seed Layers in HAR TSVs 2010 ·ECS Transactions ·Silvia Armini, Chris Wilson, Alain Moussa, Alexis Franquet, Kris Vanstreels, (unknown), (unknown), Yann Civale, (unknown), (unknown), (unknown), Wouter Ruythooren	1
16	Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping 2009 ·Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen, Patrick Jaenen, Rahul Agarwal, (unknown), Philippe Soussan, Youssef Travaly, Eric Beyne	20
17	On the Mechanisms Governing Aluminum-Mediated Solid-Phase Epitaxy of Silicon 2009 ·Journal of Electronic Materials ·Yann Civale, Guglielmo Vastola, Lis K. Nanver, (unknown), Jae-Ryoung Kim	9
18	1.9 nm wide ultra-high aspect-ratio bulk-Si FinFETs 2009 ·Vladimir Jovanović, Mirko Poljak, Tomislav Suligoj, Yann Civale, Lis K. Nanver	3
19	Evaluation of Al-doped SPE ultrashallow P+N junctions for use as PNP SiGe HBT emitters 2008 ·Yann Civale, (unknown), (unknown), Lis K. Nanver, (unknown)	2
20	Ultra-low-temperature process modules for back-wafer-contacted silicon-on-glass RF/microwave technology 2008 ·Lis K. Nanver, (unknown), Yann Civale, T.L.M. Scholtes, L. La Spina, H. Schellevis, (unknown), Francesco Sarubbi, (unknown), Koen Buisman, (unknown), (unknown)	3

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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