Paresh Limaye

1.0k citations

30 papers · 523 indexed · h-index 13

Impact in

Electrical and Electronic Engineering top 10%
- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Integrated Circuits and Semiconductor Failure Analysis
Automotive Engineering top 10%
- Additive Manufacturing and 3D Printing Technologies

Papers in

Automotive Engineering 6
- Additive Manufacturing and 3D Printing Technologies 6
Electrical and Electronic Engineering 28
- Electronic Packaging and Soldering Technologies 25
- 3D IC and TSV technologies 19
- Advanced MEMS and NEMS Technologies 3

Co-authors: Bart Vandevelde Riet Labie Eric Beyne Rahul Agarwal Mario González Petar Ratchev Philippe Soussan Wenqi Zhang
Journals: Microelectronics Reliability (2 papers)IEEE Transactions on Components Packaging and Manufacturing Technology (1 paper)Journal of Electronic Materials (1 paper)IEEE Transactions on Advanced Packaging (1 paper)Journal of Applied Physics (1 paper)
Partner nations: Belgium United States Netherlands

In The Last Decade

Paresh Limaye

29 papers receiving 503 citations

Peers

Countries citing papers authored by Paresh Limaye

Since Specialization

Citations

This map shows the geographic impact of Paresh Limaye's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Paresh Limaye with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Paresh Limaye more than expected).

Fields of papers citing papers by Paresh Limaye

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Paresh Limaye. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Paresh Limaye. The network helps show where Paresh Limaye may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Paresh Limaye, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Paresh Limaye Line = papers co-authored together Paresh Limaye links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Flexible AlScN based PMUT arrays for conformal and wearable ultrasound Epimitheas Georgitzikis, Hanaa H. Elenazy, 大庭元, Federico Winer, Milind Pandit, Mariève Gendron, M. Nur, Diana Van Lancker, Zhiyuan Shen, Kimberly C Vásconez, Paresh Limaye, Fatima Farheen Nisha Chowdhury	2025	0
2	Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding Nga Pham, Vladimir Cherman, Bart Vandevelde, Paresh Limaye, F MOLFINO, Roelof Jansen, Zavier Mason, Deniz Sabuncuoglu Tezcan, Philippe Soussan, Eric Beyne, H.A.C. Tilmans	2011	6
3	Novel Cu–Cu Bonding Technique: The Insertion Bonding Approach IEEE Transactions on Components Packaging and Manufacturing Technology ·Chukwudi Okoro, Paresh Limaye, Rahul Agarwal, Bart Vandevelde, Eric Beyne, Dirk Vandepitte	2011	7
4	Design issues and cosiderations for low-cost 3D TSV IC technology Lirias (KU Leuven) ·Matthias Albrecht, Paresh Limaye, A. Mercha, Herman Oprins, C. Torregiani, S. Thijs, D. Linten, N. Vogt, 浩教一宮, Bart Vandevelde, Е. В. Андронов, Ingrid De Wolf, Riet Labie, Dan Perry	2010	6
5	Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking Riet Labie, Paresh Limaye, Kyung-Woo Lee, Koós Bálint György, Eric Beyne, Ingrid De Wolf	2010	51
6	Die-to-Wafer Bonding of Thin Dies using a 2-Step Approach; High Accuracy Placement, then Gang Bonding Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ·张清河, Rahul Agarwal, Wenqi Zhang, Paresh Limaye, Riet Labie, Alain Phommahaxay, Philippe Soussan	2010	2
7	Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions Geert Van der Plas, S. Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, A. Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, AA Mitra, Bernadette Priya Pandya-Orozco, M. Dehan, A. Schmitz, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal	2010	12
8	Cu/Sn microbumps interconnect for 3D TSV chip stacking Rahul Agarwal, Wenqi Zhang, Paresh Limaye, Riet Labie, Biljana Dimčić, Alain Phommahaxay, Philippe Soussan	2010	87
9	Thermo-mechanical design of a generic 0-level MEMS package using chip capping and Through Silicon Via's Bart Vandevelde, Roelof Jansen, S. Bouwstra, Nga Pham, Fatma Dewi Sinurat, Paresh Limaye, Eric Beyne, H.A.C. Tilmans	2010	4
10	Verifying thermal/thermo-mechanical behavior of a 3D stack — challenges and solutions Paul Marchal, Geert Van der Plas, Paresh Limaye, A. Mercha, S. Thijs, Dimitri Linten, Guruprasad Katti, Michele Stucchi, Bart Vandevelde, Stephane Bronckers, AA Mitra, Bernadette Priya Pandya-Orozco, M. Dehan, A. Schmitz, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne	2010	4
11	A Novel Mechanism of Embrittlement Affecting the Impact Reliability of Tin-Based Lead-Free Solder Joints Journal of Electronic Materials ·Konstantina Lambrinou, Wilson Lazo-Salmeron, Paresh Limaye, Bart Vandevelde, Bert Verlinden, Ingrid De Wolf	2009	23
12	High density Cu-Sn TLP bonding for 3D integration Rahul Agarwal, Wenqi Zhang, Paresh Limaye, Wouter Ruythooren	2009	31
13	An integrated creep, crack growth and thermo-mechanical fatigue model for WLCSP assemblies soldered with SAC 405 Paresh Limaye, Bart Vandevelde, Dirk Vandepitte, Bert Verlinden	2009	4
14	Influence of Intermetallic Properties on Reliability of Lead-Free Flip-Chip Solder Joints IEEE Transactions on Advanced Packaging ·Paresh Limaye, Bart Vandevelde, Riet Labie, Dirk Vandepitte, Bert Verlinden	2008	21
15	Creep Behavior of Mixed SAC 405/SnPb Soldered Assemblies in Shear Loading Lirias (KU Leuven) ·Paresh Limaye, Riet Labie, Bart Vandevelde, Dirk Vandepitte, Bert Verlinden	2007	15
16	Crack Growth Analysis of Lead Free Passive Component Assemblies Paresh Limaye, Wulandari Wijaya, Bart Vandevelde, Dirk Vandepitte, Bert Verlinden, Bart Allaert, Qingsong Song	2006	2
17	Analytical and finite element models of the thermal behavior for lead-free soldering processes in electronic assembly Microelectronics Reliability ·N. Van Steenberge, Paresh Limaye, Geert Willems, Bart Vandevelde, IABSE WG on Forensic Structural Engineering	2006	21
18	Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis Tirtharaj Purushottam Babre, Paresh Limaye, Mario González, Bart Vandevelde	2006	13
19	Crack Growth Rate Measurement and Analysis for WLCSP Sn-Ag-Cu Solder Joints Paresh Limaye, Bart Vandevelde, (unknown), (unknown)	2005	12
20	Hermal cycling reliability of snagcu and snpb solder joints: a comparison for several ic-packages Bart Vandevelde, Mario González, Paresh Limaye, Petar Ratchev, Eric Beyne	2005	12

About Paresh Limaye

Paresh Limaye is a scholar working on Automotive Engineering, Electrical and Electronic Engineering, Ceramics and Composites, Mechanical Engineering and Statistics, Probability and Uncertainty, having authored 30 papers that have together received 523 indexed citations. Recurring topics across this work include Electronic Packaging and Soldering Technologies (25 papers), 3D IC and TSV technologies (19 papers), Additive Manufacturing and 3D Printing Technologies (6 papers), Aluminum Alloys Composites Properties (5 papers), Advanced MEMS and NEMS Technologies (3 papers), Aluminum Alloy Microstructure Properties (3 papers), Advanced Welding Techniques Analysis (3 papers) and Advanced Surface Polishing Techniques (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (480 citations), Automotive Engineering (59 citations), Mechanical Engineering (177 citations), Electronic, Optical and Magnetic Materials (51 citations) and Mechanics of Materials (64 citations). Paresh Limaye has collaborated with scholars based in Belgium, United States and Netherlands. Frequent co-authors include Bart Vandevelde, Riet Labie, Eric Beyne, Rahul Agarwal, Mario González, Petar Ratchev, Philippe Soussan, Wenqi Zhang, Alain Phommahaxay and Bert Verlinden. Their work appears in journals such as Microelectronics Reliability, IEEE Transactions on Components Packaging and Manufacturing Technology, Journal of Electronic Materials, IEEE Transactions on Advanced Packaging and Journal of Applied Physics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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