A. Cros

1.3k citations

32 papers · 346 indexed · h-index 11

Impact in

Electrical and Electronic Engineering top 10%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
Hardware and Architecture

Papers in

Electrical and Electronic Engineering 32
- Advancements in Semiconductor Devices and Circuit Design 32
- Semiconductor materials and devices 32
- Integrated Circuits and Semiconductor Failure Analysis 13
- Silicon Carbide Semiconductor Technologies 5
- Low-power high-performance VLSI design 2
- Electrostatic Discharge in Electronics 2
Atomic and Molecular Physics, and Optics 3
- Surface and Thin Film Phenomena 2

Co-authors: G. Ghibaudo José M. de la Rosa X. Federspiel E. Josse Minju Shin Mireille Mouis Gyu‐Tae Kim V. Huard
Journals: Solid-State Electronics (10 papers)IEEE Transactions on Electron Devices (2 papers)Journal of Computational Electronics (1 paper)IEEE Electron Device Letters (1 paper)IEEE Transactions on Semiconductor Manufacturing (1 paper)
Partner nations: France Switzerland United States

In The Last Decade

A. Cros

30 papers receiving 340 citations

Peers

Countries citing papers authored by A. Cros

Since Specialization

Citations

This map shows the geographic impact of A. Cros's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Cros with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Cros more than expected).

Fields of papers citing papers by A. Cros

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Cros. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Cros. The network helps show where A. Cros may publish in the future.

Co-authorship network

The 25 scholars most cited alongside A. Cros, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with A. Cros Line = papers co-authored together A. Cros links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Modeling self-heating effects in advanced CMOS nodes F. Thun, A. Cros, X. Federspiel, Cheikh Ndiaye, V. Huard, M. Rafik	2018	9
2	FDSOI Mosfet gate dielectric breakdown Vd dependancy X. Federspiel, M. Rafik, F. Thun, A. Cros, F. Cacho	2018	2
3	New Y -function based MOSFET parameter extraction method from weak to strong inversion range Solid-State Electronics ·Cao Min, Quentin Rafhay, A. Cros, G. Ghibaudo	2016	21
4	BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization F. Cacho, A. Cros, X. Federspiel, V. Huard, Nitto Denko corporation	2016	5
5	A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology Fatemeh Hemmati, F. Andrieu, P. Perreau, David Cooper, Nirmodi Fadake, Olivier Gourhant, P. Rivallin, Nicolas Bernier, A. Cros, Cheikh Ndiaye, 孫嘉蘭, Sharma Pradeep, D. Dutartre, A. Claverie, O. Weber, E. Josse, M. Vinet, M. Haond	2016	3
6	In depth characterization of electron transport in 14 nm FD-SOI CMOS devices Solid-State Electronics ·Minju Shin, k Matt, Mireille Mouis, A. Cros, E. Josse, Gyu‐Tae Kim, G. Ghibaudo	2015	16
7	Low temperature characterization of mobility in 14 nm FD-SOI CMOS devices under interface coupling conditions Solid-State Electronics ·Minju Shin, k Matt, Mireille Mouis, A. Cros, E. Josse, Gyu‐Tae Kim, G. Ghibaudo	2015	22
8	Application of compact HCI model to prediction of process effect in 28FDSOI technology 炫童王, X. Federspiel, A. Bravaix, Rafael Hoppen Dos Santos, A. Cros, D. Roy	2014	10
9	Analysis of process impact on local variability thanks to addressable transistors arrays A. Cros, Thomas Quémerais, A. Bajolet, 昌光宇都宮, Liuyu Fang, Marie-Pierre Golinelli, N. Planes, D. Petit, F. Arnaud, Dongdong Li	2014	0
10	First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration Dominique Golanski, P. Fonteneau, C. Fenouillet-Béranger, A. Cros, F. Monsieur, SNEH JOSHI, Philipp Kristian Diekhöner, Maria Vitória Oliveira da Silva, 吕飞阅 Lü Feiyue, Ross L. Finney, Rafael Hoppen Dos Santos, LuuV Pham, O. Weber, O. Saxod, D Parrinder, Philippe Galy, N. Planes, F. Arnaud	2013	22
11	BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset Д А Мастеренко, V. Huard, Siti Rachmah Al-syifa, A. Cros, X. Federspiel, A. Bajolet, 昌光宇都宮, Nikolaos Siopis, Marília Duarte Silva, F. Cacho, A. Bravaix	2013	55
12	“Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction Solid-State Electronics ·Cl. Creuzet, A. Cros, S. Monfray, Jérôme Mitard, José M. de la Rosa, D. Gloria, G. Ghibaudo	2013	19
13	Unexpected impact of germanium content in SiGe bulk PMOSFETs Solid-State Electronics ·Cl. Creuzet, A. Cros, Oksana Viktorovna Shurygina, D. Rideau, S. Haendler, José M. de la Rosa, G. Ghibaudo	2013	2
14	An improved procedure to extract the limiting carrier velocity in ultra scaled CMOS devices Institutional Research Information System (University of Udine) ·P.-E. Werner, R. Clerc, Pierpaolo Palestri, Cl. Creuzet, A. Cros, David Esseni, F. Bœuf, G. Ghibaudo, L. Selmi	2012	1
15	Characterization and modeling of capacitances in FD-SOI devices Sanna Bergling, A. Cros, C. Fenouillet-Béranger, P. Perreau, A. Margain, F. Bœuf, F. Balestra, G. Ghibaudo	2011	2
16	Transport characterisation of Ge pMOSFETS in saturation regime Cl. Creuzet, A. Cros, S. Monfray, Jérôme Mitard, José M. de la Rosa, F. Bœuf, G. Ghibaudo	2011	1
17	A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs HAL (Le Centre pour la Communication Scientifique Directe) ·Dominique Fleury, A. Cros, LuuV Pham, H. Brut, E. Josse, F. L. CARSTEN	2009	5
18	Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below IEEE Transactions on Semiconductor Manufacturing ·Dominique Fleury, A. Cros, Ziyi An, David P. Roy, И.Д. Козочкин, Benjamin Dumont, H. Brut, G. Ghibaudo	2008	16
19	Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy IEEE Transactions on Nanotechnology ·M. Hofheinz, X. Jehl, M. Sanquer, Mustafa Murat Taşer, A. Cros, P. Coronel, H. Brut, T. Skotnicki	2008	1
20	Metal gate-all-around CMOS integration using poly-gate replacement through contact hole (PRETCH) Mustafa Murat Taşer, P. Coronel, S. Harrison, A. Cros, R. Wacquez, A. Pouydebasque, D. Delille, 劉真倫, S. Borel, F. Leverd, Marie-Pierre Samson, Adnan Masood, F. Balestra, T. Skotnicki	2005	0

About A. Cros

A. Cros is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Biomedical Engineering, Infectious Diseases and Organic Chemistry, having authored 32 papers that have together received 346 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (32 papers), Semiconductor materials and devices (32 papers), Integrated Circuits and Semiconductor Failure Analysis (13 papers), Silicon Carbide Semiconductor Technologies (5 papers), Low-power high-performance VLSI design (2 papers), Analog and Mixed-Signal Circuit Design (2 papers), Surface and Thin Film Phenomena (2 papers) and Electrostatic Discharge in Electronics (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (341 citations), Hardware and Architecture (20 citations), Atomic and Molecular Physics, and Optics (29 citations), Biomedical Engineering (36 citations) and Condensed Matter Physics (7 citations). A. Cros has collaborated with scholars based in France, Switzerland and United States. Frequent co-authors include G. Ghibaudo, José M. de la Rosa, X. Federspiel, E. Josse, Minju Shin, Mireille Mouis, Gyu‐Tae Kim, V. Huard, A. Bravaix and F. Cacho. Their work appears in journals such as Solid-State Electronics, IEEE Transactions on Electron Devices, Journal of Computational Electronics, IEEE Electron Device Letters and IEEE Transactions on Semiconductor Manufacturing.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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