C. Auth

5.9k total citations · 1 hit paper
17 papers, 1.8k citations indexed

About

C. Auth is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Electronic, Optical and Magnetic Materials. According to data from OpenAlex, C. Auth has authored 17 papers receiving a total of 1.8k indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 5 papers in Biomedical Engineering and 2 papers in Electronic, Optical and Magnetic Materials. Recurrent topics in C. Auth's work include Semiconductor materials and devices (16 papers), Advancements in Semiconductor Devices and Circuit Design (14 papers) and Nanowire Synthesis and Applications (5 papers). C. Auth is often cited by papers focused on Semiconductor materials and devices (16 papers), Advancements in Semiconductor Devices and Circuit Design (14 papers) and Nanowire Synthesis and Applications (5 papers). C. Auth collaborates with scholars based in United States. C. Auth's co-authors include J.D. Plummer, K. Mistry, T. Ghani, M Armstrong, A. Murthy, M. Bohr, Scott E. Thompson, S. Sivakumar, B. McIntyre and G. Glass and has published in prestigious journals such as Applied Physics Letters, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.

In The Last Decade

C. Auth

16 papers receiving 1.7k citations

Hit Papers

Scaling theory for cylind... 1997 2026 2006 2016 1997 100 200 300 400

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author Last Decade Papers Cites
C. Auth 1.7k 464 186 186 49 17 1.8k
A. Murthy 1.5k 0.9× 415 0.9× 204 1.1× 191 1.0× 18 0.4× 13 1.6k
K. Rim 1.5k 0.9× 382 0.8× 281 1.5× 367 2.0× 47 1.0× 41 1.7k
Liesbeth Witters 1.7k 1.0× 326 0.7× 226 1.2× 156 0.8× 15 0.3× 148 1.7k
Meishoku Masahara 2.4k 1.5× 371 0.8× 200 1.1× 204 1.1× 53 1.1× 232 2.5k
A. Khakifirooz 1.0k 0.6× 297 0.6× 144 0.8× 227 1.2× 27 0.6× 67 1.1k
B. Obradovic 1.1k 0.6× 347 0.7× 227 1.2× 455 2.4× 22 0.4× 37 1.3k
A. De Keersgieter 1.7k 1.0× 240 0.5× 124 0.7× 97 0.5× 21 0.4× 117 1.7k
M Armstrong 1.2k 0.7× 348 0.8× 160 0.9× 133 0.7× 10 0.2× 14 1.3k
Jérôme Mitard 3.1k 1.8× 461 1.0× 370 2.0× 350 1.9× 57 1.2× 234 3.1k
R. Rooyackers 2.7k 1.6× 671 1.4× 294 1.6× 117 0.6× 11 0.2× 189 2.8k

Countries citing papers authored by C. Auth

Since Specialization
Citations

This map shows the geographic impact of C. Auth's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Auth with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Auth more than expected).

Fields of papers citing papers by C. Auth

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Auth. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Auth. The network helps show where C. Auth may publish in the future.

Co-authorship network of co-authors of C. Auth

This figure shows the co-authorship network connecting the top 25 collaborators of C. Auth. A scholar is included among the top collaborators of C. Auth based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. Auth. C. Auth is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

17 of 17 papers shown
1.
Auth, C., et al.. (2023). Evolution of Transistors: Humble Beginnings to the Ubiquitous Present. IEEE Solid-State Circuits Magazine. 15(3). 20–28. 5 indexed citations
2.
Avci, Uygar E., R. Grover, J. Hicks, et al.. (2020). Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process. 1–4. 11 indexed citations
3.
Wang, Xinning, Ravi Kumar, Peng Zheng, et al.. (2018). Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process. 28.2.1–28.2.4. 12 indexed citations
4.
Griggio, Flavio, J. Palmer, Nikholas G. Toledo, et al.. (2018). Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology. 6E.3–1. 44 indexed citations
5.
Prasad, C., M. Agostinelli, J. Hicks, et al.. (2014). Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures. 6A.5.1–6A.5.7. 34 indexed citations
6.
Ramey, S., C. Auth, Jason Clifford, et al.. (2013). Intrinsic transistor reliability improvements from 22nm tri-gate technology. 4C.5.1–4C.5.5. 137 indexed citations
7.
Auth, C.. (2012). 22-nm fully-depleted tri-gate CMOS transistors. 1–6. 56 indexed citations
8.
Tyagi, S., C. Auth, Ibrahim Ban, et al.. (2009). Future device scaling - Beyond traditional CMOS. 1–4. 1 indexed citations
9.
Auth, C.. (2008). 45nm high-k + metal gate strain-enhanced CMOS transistors. 379–386. 28 indexed citations
10.
Ghani, T., M Armstrong, C. Auth, et al.. (2004). A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. 11.6.1–11.6.3. 378 indexed citations
11.
Mistry, K., M Armstrong, C. Auth, et al.. (2004). Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology. 50–51. 114 indexed citations
12.
Shifren, L., Philippe Matagne, B. Obradovic, et al.. (2004). Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress. Applied Physics Letters. 85(25). 6188–6190. 24 indexed citations
13.
Giles, M.D., M Armstrong, C. Auth, et al.. (2004). Understanding stress enhanced performance in Intel 90nm CMOS technology. 118–119. 21 indexed citations
14.
Thompson, Scott E., M Armstrong, C. Auth, et al.. (2004). A Logic Nanotechnology Featuring Strained-Silicon. IEEE Electron Device Letters. 25(4). 191–193. 389 indexed citations
15.
Auth, C. & J.D. Plummer. (2002). Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 μm thick silicon pillars. 108–109. 13 indexed citations
16.
Auth, C. & J.D. Plummer. (1998). A simple model for threshold voltage of surrounding-gate MOSFET's. IEEE Transactions on Electron Devices. 45(11). 2381–2383. 62 indexed citations
17.
Auth, C. & J.D. Plummer. (1997). Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Device Letters. 18(2). 74–76. 431 indexed citations breakdown →

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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