J. Hicks

3.0k citations

40 papers · 681 indexed · h-index 14

Hardware and Architecture top 5%
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices 22
- Integrated Circuits and Semiconductor Failure Analysis 17
- Advancements in Semiconductor Devices and Circuit Design 16
- Ferroelectric and Negative Capacitance Devices 6
- Advanced Memory and Neural Computing 4
- Electrostatic Discharge in Electronics 4
Electronic, Optical and Magnetic Materials
- Copper Interconnects and Reliability 5
Geometry and Topology
- Algebraic Geometry and Number Theory 5
Safety, Risk, Reliability and Quality

Co-authors: S. Ramey C. Auth C. Prasad Robert B. Miller Anisur Rahman M. Hattendorf S. Novak A. St. Amour
Cited by: Hardware and Architecture Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials
Journals: IEEE Transactions on Device and Materials Reliability (1 paper)Geometry & Topology (1 paper)Journal of Topology (1 paper)
Partner nations: United States United Kingdom Greece

In The Last Decade

J. Hicks

38 papers receiving 652 citations

Peers

Countries citing papers authored by J. Hicks

Since Specialization

Citations

This map shows the geographic impact of J. Hicks's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Hicks with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Hicks more than expected).

Fields of papers citing papers by J. Hicks

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Hicks. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Hicks. The network helps show where J. Hicks may publish in the future.

Co-authorship network

The 25 scholars most cited alongside J. Hicks, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Hicks Line = papers co-authored together J. Hicks links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Microprocessor Switching Activity Translation to AC Gate Oxide Wearout: Does it Matter? INTEL4 Meteor Lake Chip Activity Case Study L. Pantisano,Seung ho Lee,Z. Chbili,صبا اصغر زاده,S. Ramey,J. Hicks,Hung V. Le,Waeuseng Nurkamilasari,M. Fazio,Wesley A. Belli	2025	0
2	Realizability in tropical geometry and unobstructedness of Lagrangian submanifolds Geometry & Topology ·J. Hicks	2025	0
3	Wall-crossing from Lagrangian cobordisms Algebraic & Geometric Topology ·J. Hicks	2024	1
4	Resolutions of toric subvarieties by line bundles and applications SHILAP Revista de lepidopterología ·سمیه جنت رستمی,J. Hicks,ávila Briceño	2024	3
5	A short computation of the Rouquier dimension for a cycle of projective lines St Andrews Research Repository (St Andrews Research Repository) ·سمیه جنت رستمی,J. Hicks	2024	1
6	Lagrangian cobordisms and Lagrangian surgery Commentarii Mathematici Helvetici ·J. Hicks	2023	1
7	Reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes Dr.M.V. Sudhamani,Chuang Lin,전주교육대학교,J. Palmer,Andrés Mauricio Osorio Vinasco,G N Gregor Nelles,J. R. Weber,Charles H. Wallace,J. Hicks	2023	1
8	Tropical Lagrangian hypersurfaces are unobstructed Journal of Topology ·J. Hicks	2020	9
9	eNVM MRAM Retention Reliability Modeling in 22FFL FinFET Technology Chi Xinxi,Chris Connor,Tanmoy Pramanik,J. Hicks,Juan G. Alzate,Fatih Hamzaoglu,Justin Brockman,O. Golonzka,L.M. Anderson	2019	6
10	Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology Flavio Griggio,J. Palmer,Eko March Handoko Bin Masyhur,Nikholas G. Toledo,Karina Elizabeth Bravo,A.K. Przyby,Dr.M.V. Sudhamani,G. Leatherman,J. Hicks,Advait Madhavan,Khaled Madhoun,Joseph M. Steigerwald,A. Yeoh,C. Auth	2018	44
11	Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors IEEE Transactions on Nuclear Science ·N. Seifert,Shah M. Jahinuzzaman,Jyothi Velamala,Ricardo Ascázubi,Joan F. McDonald,B. Gill,Natalya Suptelo,J. Hicks	2015	83
12	SILC and gate oxide breakdown characterization of 22nm tri-gate technology S. Ramey,J. Hicks	2014	3
13	Intrinsic transistor reliability improvements from 22nm tri-gate technology S. Ramey,Diane Figueredo da Silva,C. Auth,Jason Clifford,M. Hattendorf,J. Hicks,R. James,Anisur Rahman,Abhishek Nath,A. St. Amour,C. Wiegand	2013	137
14	Low-k ILD reliability through chip-package assembly: Engineering appropriate stress tests and process certification criteria Sudarshan Rangaraj,J. Hicks,Zusanti Zusanti,Marí R. Carreras,Priambudi Renardi Adryantoro,Anisa Ammar,A. Schrauf,Guotao Wang	2013	1
15	Transistor Performance Impact Due to Die–Package Mechanical Stress IEEE Transactions on Device and Materials Reliability ·G. Leatherman,J. Hicks,Bahattin Kilic,Daniel Pantuso,郭瑞友	2013	5
16	Die-package stress interaction impact on transistor performance G. Leatherman,Mcmahon Benjamin,J. Hicks,Bahattin Kilic,Daniel Pantuso	2012	16
17	Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging Dr.M.V. Sudhamani,Chris Connor,J. Hicks,J. Jopling,GIOVANNA AZEVEDO RODRIGUES	2009	5
18	Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology Sangwoo Pae,T. Ghani,M. Hattendorf,J. Hicks,J. Jopling,J. Maiz,K. Mistry,Chi Xinxi,C. Prasad,Jami Wiedemer,Jian Xu	2009	10
19	Microprocessor reliability performance as a function of die location for a 0.25 μ, five layer metal CMOS logic process Teonila Álvarez Echevarría,Robert B. Miller,Jamie Sherman,J. Hicks	2003	49
20	Reliability versus yield and die location in advanced VLSI Microelectronics Reliability ·Teonila Álvarez Echevarría,Robert B. Miller,J. Hicks	1999	5

About J. Hicks

J. Hicks is a scholar working on Geometry and Topology, Electrical and Electronic Engineering and Mathematical Physics, having authored 40 papers that have together received 681 indexed citations. Recurring topics across this work include Semiconductor materials and devices (22 papers), Integrated Circuits and Semiconductor Failure Analysis (17 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Ferroelectric and Negative Capacitance Devices (6 papers), Algebraic Geometry and Number Theory (5 papers), Copper Interconnects and Reliability (5 papers), Advanced Memory and Neural Computing (4 papers) and Electrostatic Discharge in Electronics (4 papers). The work is most often cited by research in Hardware and Architecture (93 citations), Electrical and Electronic Engineering (635 citations) and Electronic, Optical and Magnetic Materials (56 citations). J. Hicks has collaborated with scholars based in United States, United Kingdom and Greece. Frequent co-authors include S. Ramey, C. Auth, C. Prasad, Robert B. Miller, Anisur Rahman, M. Hattendorf, S. Novak, A. St. Amour, R. James and C. Wiegand. Their work appears in journals such as IEEE Transactions on Device and Materials Reliability, Geometry & Topology, Journal of Topology, Algebraic & Geometric Topology and Commentarii Mathematici Helvetici.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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