J. Kavalieros

5.1k total citations · 1 hit paper
41 papers, 3.6k citations indexed

About

J. Kavalieros is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Materials Chemistry. According to data from OpenAlex, J. Kavalieros has authored 41 papers receiving a total of 3.6k indexed citations (citations by other indexed papers that have themselves been cited), including 39 papers in Electrical and Electronic Engineering, 10 papers in Biomedical Engineering and 4 papers in Materials Chemistry. Recurrent topics in J. Kavalieros's work include Semiconductor materials and devices (36 papers), Advancements in Semiconductor Devices and Circuit Design (33 papers) and Integrated Circuits and Semiconductor Failure Analysis (10 papers). J. Kavalieros is often cited by papers focused on Semiconductor materials and devices (36 papers), Advancements in Semiconductor Devices and Circuit Design (33 papers) and Integrated Circuits and Semiconductor Failure Analysis (10 papers). J. Kavalieros collaborates with scholars based in United States and Belgium. J. Kavalieros's co-authors include R. Chau, Suman Datta, M. Doczy, Barry M. Doyle, M. Metz, M. Radosavljević, B.S. Doyle, G. Dewey, B. Jin and Kevin S. Zhang and has published in prestigious journals such as Nature Materials, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.

In The Last Decade

J. Kavalieros

38 papers receiving 3.4k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

2005 510 citations Suman Datta, M. Doczy et al. profile →

Peers

Countries citing papers authored by J. Kavalieros

Since Specialization

Citations

This map shows the geographic impact of J. Kavalieros's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Kavalieros with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Kavalieros more than expected).

Fields of papers citing papers by J. Kavalieros

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Kavalieros. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Kavalieros. The network helps show where J. Kavalieros may publish in the future.

Co-authorship network of co-authors of J. Kavalieros

This figure shows the co-authorship network connecting the top 25 collaborators of J. Kavalieros. A scholar is included among the top collaborators of J. Kavalieros based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Kavalieros. J. Kavalieros is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	FeRAM Capacitor with Novel Low-Power, Non-destructive and High Endurance Read operation for High-density Embedded Memory 2025 ·Shahbaz Ahmed Siddiqui, Sou-Chi Chang, (unknown), (unknown), (unknown), (unknown), Gyu-Yeong Choe, (unknown), (unknown), M. Metz, J. Kavalieros, Uygar E. Avci	1
2	Beyond RibbonFET: Energy Efficiency Innovations to Drive Technology and Design for the Next Decade 2025 ·Chung-Hsun Lin, B. Greene, Hai Li, Raseong Kim, J. Kavalieros, T. Ghani	0
3	Multi-domain Phase-field Modeling of Polycrystalline Hafnia-based (Anti-)ferroelectrics Capable of Representing Defects, Wake-up and Fatigue 2022 ·2022 International Electron Devices Meeting (IEDM) ·Sou-Chi Chang, (unknown), M. Popovici, Chia‐Ching Lin, Saima Siddiqui, I‐Cheng Tung, (unknown), (unknown), Nazila Haratipour, M. Metz, J. Kavalieros, Gouri Sankar Kar, Andrew C. Kummel, Kyeongjae Cho, Uygar E. Avci	4
4	Gate-All-Around Strained Si_0.4Ge_0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application 2020 ·Ankur Agrawal, S. Chouksey, W. Rachmady, Suresh Vishwanath, (unknown), (unknown), J. Torres, A. Oni, X. Weng, (unknown), Devin R. Merrill, M. Metz, A. Murthy, J. Kavalieros	40
5	Anti-ferroelectric Hf_xZr_1-xO₂ Capacitors for High-density 3-D Embedded-DRAM 2020 ·Sou-Chi Chang, Nazila Haratipour, Shriram Shivaraman, (unknown), (unknown), Chia-Ching Lin, I‐Cheng Tung, Devin R. Merrill, Huiying Liu, (unknown), Fatih Hamzaoglu, M. Metz, Ian A. Young, J. Kavalieros, Uygar E. Avci	27
6	Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET 2015 ·Uygar E. Avci, B. Chu-Kung, Ashish Agrawal, G. Dewey, Hung V. Le, Rafael Rios, Daniel H. Morris, Sayed Hasan, R. Kotlyar, J. Kavalieros, Ian A. Young	36
7	High-/Metal–Gate Stack and Its MOSFET Characteristics 2014 ·(unknown), (unknown), Suman Datta, M. Doczy, Barry M. Doyle, J. Kavalieros, (unknown)	0
8	Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al<inf>0.83</inf>In<inf>0.17</inf>N/AlN/GaN MOS-HEMT on SiC substrate 2013 ·Han Wui Then, Sandeepan DasGupta, M. Radosavljević, (unknown), B. Chu-Kung, G. Dewey, (unknown), Xiaoqin Gao, J. Kavalieros, Niloy Mukherjee, M. Metz, Matthew J. Oliver, R. Pillarisetty, Valluri Rao, Seung-Hun Sung, Guanhua Yang, R. Chau	21
9	Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications 2010 ·M. Radosavljević, G. Dewey, J. M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, (unknown), Niloy Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, Uday Shah, R. Chau	78
10	Advanced high-K gate dielectric for high-performance short-channel In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum well field effect transistors on silicon substrate for low power logic applications 2009 ·M. Radosavljević, B. Chu-Kung, S. Corcoran, G. Dewey, Mantu K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, (unknown), Niloy Mukherjee, W. Rachmady, Uday Shah, R. Chau	111
11	Integrated nanoelectronics for the future 2007 ·Nature Materials ·R. Chau, B.S. Doyle, Suman Datta, J. Kavalieros, Kevin S. Zhang	327
12	Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology 2005 ·Microelectronic Engineering ·R. Chau, (unknown), Suman Datta, G. Dewey, M. Doczy, B.S. Doyle, J. Kavalieros, B. Jin, M. Metz, Amlan Majumdar, M. Radosavljević	104
13	High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack 2004 ·Suman Datta, G. Dewey, M. Doczy, B.S. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, (unknown), R. Chau	65
14	Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout 2004 ·Barry M. Doyle, B. I. Boyanov, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau	163
15	High-<tex>$kappa$</tex>/Metal–Gate Stack and Its MOSFET Characteristics 2004 ·IEEE Electron Device Letters ·R. Chau, Suman Datta, M. Doczy, Barry M. Doyle, J. Kavalieros, M. Metz	365
16	A 50 nm depleted-substrate CMOS transistor (DST) 2002 ·R. Chau, J. Kavalieros, Barry M. Doyle, A. Murthy, (unknown), (unknown), Douglas W. Barlage, Reza Arghavani, B. Roberds, M. Doczy	73
17	Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate 2002 ·R. Chau, B.S. Doyle, J. Kavalieros, (unknown), A. Murthy, M. Doczy, Reza Arghavani, Suman Datta	49
18	Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit 2000 ·IEEE Electron Device Letters ·Douglas W. Barlage, (unknown), J. Kavalieros, Manh-Cuong Nguyen, R. Chau	40
19	Separation of interface and nonuniform oxide traps by the DC current-voltage method 1996 ·IEEE Transactions on Electron Devices ·J. Kavalieros, Chih‐Tang Sah	11
20	Profiling interface traps in MOS transistors by the DC current-voltage method 1996 ·IEEE Electron Device Letters ·Chih‐Tang Sah, A. Neugroschel, Ki-Lim Han, J. Kavalieros	19

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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