A. Murthy

3.8k total citations
13 papers, 1.6k citations indexed

About

A. Murthy is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Computer Networks and Communications. According to data from OpenAlex, A. Murthy has authored 13 papers receiving a total of 1.6k indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Electrical and Electronic Engineering, 4 papers in Biomedical Engineering and 1 paper in Computer Networks and Communications. Recurrent topics in A. Murthy's work include Advancements in Semiconductor Devices and Circuit Design (12 papers), Semiconductor materials and devices (12 papers) and Nanowire Synthesis and Applications (4 papers). A. Murthy is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (12 papers), Semiconductor materials and devices (12 papers) and Nanowire Synthesis and Applications (4 papers). A. Murthy collaborates with scholars based in United States, United Kingdom and India. A. Murthy's co-authors include R. Chau, J. Kavalieros, T. Ghani, M. Doczy, M Armstrong, M. Bohr, Scott E. Thompson, C. Auth, K. Mistry and S. Sivakumar and has published in prestigious journals such as SAE technical papers on CD-ROM/SAE technical paper series, IEEE Electron Device Letters and ECS Transactions.

In The Last Decade

A. Murthy

13 papers receiving 1.5k citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author						Papers	Cites
A. Murthy	1.5k	415	204	191	26	13	1.6k
M Armstrong	1.2k 0.8×	348 0.8×	160 0.8×	133 0.7×	24 0.9×	14	1.3k
T. Poiroux	2.0k 1.3×	458 1.1×	181 0.9×	109 0.6×	24 0.9×	125	2.1k
R. Rooyackers	2.7k 1.8×	671 1.6×	294 1.4×	117 0.6×	20 0.8×	189	2.8k
A. De Keersgieter	1.7k 1.1×	240 0.6×	124 0.6×	97 0.5×	13 0.5×	117	1.7k
M. Cassé	2.0k 1.3×	501 1.2×	289 1.4×	151 0.8×	9 0.3×	178	2.1k
Srikanth Samavedam	1.3k 0.9×	361 0.9×	714 3.5×	289 1.5×	26 1.0×	42	1.5k
S. Tyagi	773 0.5×	193 0.5×	157 0.8×	122 0.6×	28 1.1×	18	835
E. Augendre	1.3k 0.8×	286 0.7×	446 2.2×	144 0.8×	13 0.5×	110	1.4k
Philippe Matagne	937 0.6×	334 0.8×	350 1.7×	417 2.2×	11 0.4×	73	1.3k
Andriy Hikavyy	1.3k 0.9×	383 0.9×	260 1.3×	224 1.2×	18 0.7×	152	1.4k

Countries citing papers authored by A. Murthy

Since Specialization

Citations

This map shows the geographic impact of A. Murthy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Murthy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Murthy more than expected).

Fields of papers citing papers by A. Murthy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Murthy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Murthy. The network helps show where A. Murthy may publish in the future.

Co-authorship network of co-authors of A. Murthy

This figure shows the co-authorship network connecting the top 25 collaborators of A. Murthy. A scholar is included among the top collaborators of A. Murthy based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with A. Murthy. A. Murthy is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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13 of 13 papers shown

Agrawal, Ankur, S. Chouksey, W. Rachmady, et al.. (2020). Gate-All-Around Strained Si_0.4Ge_0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application. 2.2.1–2.2.4. 40 indexed citations

Kuhn, Kelin J., A. Murthy, R. Kotlyar, & Markus Kühn. (2010). (Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling. ECS Transactions. 33(6). 3–17. 63 indexed citations

Kuhn, Kelin J. & A. Murthy. (2010). Past, Present and Future: SiGe and CMOS Transistor Scaling. ECS Meeting Abstracts. MA2010-02(30). 1853–1853. 22 indexed citations

Murthy, A., et al.. (2010). Improvement in Noise Transmission Across Firewall of a Passenger Car. SAE technical papers on CD-ROM/SAE technical paper series. 1. 2 indexed citations

Packan, P., S. Cea, H. Deshpande, et al.. (2008). High performance Hi-K + metal gate strain enhanced transistors on (110) silicon. 1–4. 44 indexed citations

Ghani, T., M Armstrong, C. Auth, et al.. (2004). A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. 11.6.1–11.6.3. 378 indexed citations

Mistry, K., M Armstrong, C. Auth, et al.. (2004). Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology. 50–51. 114 indexed citations

Thompson, Scott E., M Armstrong, C. Auth, et al.. (2004). A Logic Nanotechnology Featuring Strained-Silicon. IEEE Electron Device Letters. 25(4). 191–193. 389 indexed citations

Doyle, B.S., Suman Datta, M. Doczy, et al.. (2003). High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters. 24(4). 263–265. 324 indexed citations

10.

Chau, R., J. Kavalieros, Barry M. Doyle, et al.. (2002). A 50 nm depleted-substrate CMOS transistor (DST). 29.1.1–29.1.4. 73 indexed citations

11.

Chau, R., B.S. Doyle, J. Kavalieros, et al.. (2002). Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate. 49 indexed citations

12.

Barlage, Douglas W., Reza Arghavani, G. Dewey, et al.. (2002). High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics. 10.6.1–10.6.4. 29 indexed citations

13.

Chau, R., J. Kavalieros, B. Roberds, et al.. (2002). 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays. 45–48. 81 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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