S. Mudanai

1.3k citations

37 papers · 835 indexed · h-index 16

Impact in

Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Silicon Carbide Semiconductor Technologies
- Advanced Memory and Neural Computing
Hardware and Architecture top 10%
- VLSI and Analog Circuit Testing

Papers in

Electrical and Electronic Engineering 36
- Advancements in Semiconductor Devices and Circuit Design 34
- Semiconductor materials and devices 32
- Integrated Circuits and Semiconductor Failure Analysis 12
- Silicon Carbide Semiconductor Technologies 5
- Ferroelectric and Negative Capacitance Devices 4
- Low-power high-performance VLSI design 3
- VLSI and FPGA Design Techniques 2
Hardware and Architecture 3
- VLSI and Analog Circuit Testing 3

Co-authors: M.D. Giles R. Kotlyar D. Becher Kelin J. Kuhn A. Kornfeld A.F. Tasch Tan Kiat Sean A. Maheshwari
Journals: IEEE Transactions on Electron Devices (15 papers)IEEE Electron Device Letters (3 papers)Superlattices and Microstructures (1 paper)TechConnect Briefs (1 paper)
Partner nations: United States Greece

In The Last Decade

S. Mudanai

36 papers receiving 796 citations

Peers

Countries citing papers authored by S. Mudanai

Since Specialization

Citations

This map shows the geographic impact of S. Mudanai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Mudanai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Mudanai more than expected).

Fields of papers citing papers by S. Mudanai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Mudanai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Mudanai. The network helps show where S. Mudanai may publish in the future.

Co-authorship network

The 25 scholars most cited alongside S. Mudanai, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S. Mudanai Line = papers co-authored together S. Mudanai links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Role of correlation in systematic variation modeling A. Roy, Sourabh Dongaonkar, S. Mudanai	2019	1
2	An Improved Flicker Noise Model for Circuit Simulations IEEE Transactions on Electron Devices ·A. Roy, Sungwon Kim, S. Mudanai	2017	9
3	High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology M.D. Giles, Gregory Allan Carthan, D. Becher, A. Kornfeld, Oliver Ehmer, S. Mudanai, S. Natarajan, P. Newman, P. Packan, Titash Rakshit	2015	38
4	Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C. Prasad, M. Agostinelli, J. Hicks, S. Ramey, C. Auth, K. Mistry, S. Natarajan, P. Packan, I. Post, 恵一小柳, M.D. Giles, Sarthak Gupta, S. Mudanai, Kelin J. Kuhn	2014	34
5	Mechanism of Long-Channel Drain-Induced Barrier Lowering in Halo MOSFETs IEEE Transactions on Electron Devices ·A. Roy, S. Mudanai, M. Stettler	2011	16
6	Capacitance Compact Model for Ultrathin Low-Electron-Effective-Mass Materials IEEE Transactions on Electron Devices ·S. Mudanai, A. Roy, R. Kotlyar, Titash Rakshit, M. Stettler	2011	34
7	Compressive Uniaxial Stress Bandstructure Engineering for Transferred-Hole Devices IEEE Electron Device Letters ·R. Kotlyar, M.D. Giles, S. Mudanai, Kelin J. Kuhn, Meera Stephen, T. Linton, R. Pillarisetty	2010	2
8	Halo Doping: Physical Effects and Compact Modeling TechConnect Briefs ·Lee Sw, S. Mudanai, P. Packan, R. Rios, A. L. Vovsi-Kol'shtein	2006	2
9	Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs IEEE Transactions on Electron Devices ·S. Mudanai, W.-K. Shih, R. Rios, Р.И. Мачинская, Matti Kiran Sastry, Kelin J. Kuhn, P. Packan	2006	15
10	Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks IEEE Transactions on Electron Devices ·Fei Li, S. Mudanai, Hee Na Kim, Leonard F. Register, Sanjay K. Banerjee	2006	29
11	An efficient surface potential solution algorithm for compact MOSFET models R. Rios, S. Mudanai, Jing Geng, P. Packan	2005	26
12	Compact model of MOSFET electron tunneling current through ultra-thin SiO/sub 2/ and high-k gate stacks Fei Li, S. Mudanai, Hee Na Kim, Leonard F. Register, Siddhartha Banerjee	2004	4
13	A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO/sub 2//high-K gate stacks Fei Li, S. Mudanai, Hee Na Kim, Wei Zhao, Leonard F. Register, Siddhartha Banerjee	2004	3
14	A three-transistor threshold voltage model for halo processes R. Rios, Jing Geng, A. Shah, S. Mudanai, P. Packan, 陽介金森, K. Mistry	2003	34
15	Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs D.L. Kencke, Aurilene de Macêdo Alves Bona, Yuanyuan Yu, S. Mudanai, Q. Ouyang, A.F. Tasch, Siddhartha Banerjee	2003	10
16	A new and accurate quantum mechanical compact model for NMOS gate capacitance S. Mudanai, Leonard F. Register, A.F. Tasch, Siddhartha Banerjee	2002	2
17	Modeling of direct tunneling current through gate dielectric stacks S. Mudanai, AliKHushi Allami, Q. Ouyang, A.F. Tasch, Ulisy Syarifati, Dim‐Lee Kwong, Siddhartha Banerjee	2002	1
18	Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs IEEE Electron Device Letters ·S. Mudanai, Leonard F. Register, A.F. Tasch, Siddhartha Banerjee	2001	45
19	Models for electron and hole mobilities in MOS accumulation layers IEEE Transactions on Electron Devices ·S. Mudanai, G. Chindalore, W.-K. Shih, Juliana Possebon Scalari, Q. Ouyang, A.F. Tasch, C.M. Maziar, Sanjay K. Banerjee	1999	23
20	An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers IEEE Transactions on Electron Devices ·G. Chindalore, Abdulla Alakour, S. Mudanai, S.A. Hareland, W.-K. Shih, Ma Teresa Román Pérez, A.F. Tasch, C.M. Maziar	1998	9

About S. Mudanai

S. Mudanai is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Atomic and Molecular Physics, and Optics, Condensed Matter Physics and Biomedical Engineering, having authored 37 papers that have together received 835 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (34 papers), Semiconductor materials and devices (32 papers), Integrated Circuits and Semiconductor Failure Analysis (12 papers), Silicon Carbide Semiconductor Technologies (5 papers), Ferroelectric and Negative Capacitance Devices (4 papers), VLSI and Analog Circuit Testing (3 papers), Low-power high-performance VLSI design (3 papers) and VLSI and FPGA Design Techniques (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (809 citations), Hardware and Architecture (77 citations), Atomic and Molecular Physics, and Optics (92 citations), Biomedical Engineering (78 citations) and Condensed Matter Physics (13 citations). S. Mudanai has collaborated with scholars based in United States and Greece. Frequent co-authors include M.D. Giles, R. Kotlyar, D. Becher, Kelin J. Kuhn, A. Kornfeld, A.F. Tasch, Tan Kiat Sean, A. Maheshwari, Pramod Kolar and Leonard F. Register. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Superlattices and Microstructures and TechConnect Briefs.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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