L.T. Su

1.7k citations

31 papers · 1.1k indexed · h-index 14

Electrical and Electronic Engineering top 5%
- Advancements in Semiconductor Devices and Circuit Design 24
- Semiconductor materials and devices 24
- Silicon Carbide Semiconductor Technologies 12
- Integrated Circuits and Semiconductor Failure Analysis 5
- Low-power high-performance VLSI design 4
- 3D IC and TSV technologies 3
- Ferroelectric and Negative Capacitance Devices 2
Electronic, Optical and Magnetic Materials
Hardware and Architecture top 10%
Materials Chemistry
- Thermal properties of materials 3
Mechanics of Materials

Co-authors: D.A. Antoniadis J.E. Chung M. I. Flik Kenneth E. Goodson M. Sherony R. Goldblatt R. Schulz R. Wachnik
Cited by: Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials Hardware and Architecture
Journals: IEEE Electron Device Letters (7 papers)IEEE Transactions on Electron Devices (3 papers)Journal of Heat Transfer (2 papers)
Partner nations: United States China Germany

In The Last Decade

L.T. Su

29 papers receiving 1.0k citations

Peers

Countries citing papers authored by L.T. Su

Since Specialization

Citations

This map shows the geographic impact of L.T. Su's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by L.T. Su with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites L.T. Su more than expected).

Fields of papers citing papers by L.T. Su

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by L.T. Su. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by L.T. Su. The network helps show where L.T. Su may publish in the future.

Co-authorship network

The 25 scholars most cited alongside L.T. Su, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with L.T. Su Line = papers co-authored together L.T. Su links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Multi-order optical differentiator integrated with an omnidirectionally selective subtracter Applied Physics Letters ·L.T. Su,Moritaka Ogido,未知子外山,C. Xu,Wei Hu	2025	0
2	Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance Micromachines ·Ujwala Kawade,Ying Liu,Yuan Wang,Rongsheng Cai,L.T. Su	2023	4
3	“Architecting the future through heterogeneous computing” L.T. Su	2013	9
4	Optimization of series resistance in sub-0.2 μm SOI MOSFETs L.T. Su,M. Sherony,Hang Hu,J.E. Chung,D.A. Antoniadis	2002	11
5	Tradeoffs of current drive vs. short-channel effect in deep-submicrometer bulk and SOI MOSFETs L.T. Su,María el Rocío Reyero Saavedra,Daniel Dahlgren,M. Sherony,A. Wei,D.A. Antoniadis	2002	4
6	Channel and source/drain engineering in high-performance sub-0.1 μm NMOSFETs using X-ray lithography Hang Hu,L.T. Su,Insoon Yang,D.A. Antoniadis,Henry I. Smith	2002	1
7	High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay M. Hargrove,S. Crowder,E. Nowak,Wang Zhao-yua,L.K. Han,S. Moreno Alcalde,A. Ray,D. Sinitsky,DeCausey,F Guarin,James Oberschmidt,E.F. Crabbé,D. S. Yee,L.T. Su	2002	26
8	Minimization of threshold voltage variation in SOI MOSFETs M. Sherony,L.T. Su,J.E. Chung,D.A. Antoniadis	2002	6
9	Short-channel effects in deep-submicrometer SOI MOSFETS L.T. Su,Daniel Dahlgren,J.E. Chung,D.A. Antoniadis	2002	9
10	Modeling the I-V characteristics of fully-depleted SOI MOSFETs including self-heating N.D. Arora,L.T. Su,B.S. Doyle,D.A. Antoniadis	2002	6
11	Full copper wiring in a sub-0.25 μm CMOS ULSI technology D. Edelstein,J. Heidenreich,R. Goldblatt,W. Cote,Cyprian Uzoh,N. Lustig,P. Roper,T.L. McDevitt,Deng Zhen-n,A. Simon,John Dukovic,R. Wachnik,H. Rathore,R. Schulz,L.T. Su,S. Luce,John M. Slattery	2002	196
12	FP 15.6: A 480MHz RISC Microprocessor in a 0.12pm Le, CMOS Technology with Copper Interconnects Norman J. Rohrer,Ruth McIsaac,S.P. Saxena,Assunta Borzachiello,M SIMREN,Raymond E. Floyd,S. Geißler,Berpikir Kritis,R. Houle,Minghui Zhen,楓介須賀,Thomas Francis Morley,L.T. Su,A. Punitha	1998	3
13	A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET IEEE Electron Device Letters ·Ralph W. Young,L.T. Su,M. Ieong,Sharad Kapur	1998	6
14	Reduction of threshold voltage sensitivity in SOI MOSFET's IEEE Electron Device Letters ·M. Sherony,L.T. Su,J.E. Chung,D.A. Antoniadis	1995	21
15	Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits Journal of Heat Transfer ·Kenneth E. Goodson,M. I. Flik,L.T. Su,D.A. Antoniadis	1995	31
16	A study of deep-submicron MOSFET scaling based on experiment and simulation IEEE Transactions on Electron Devices ·María el Rocío Reyero Saavedra,Daniel Dahlgren,L.T. Su,D.A. Antoniadis	1995	48
17	Measurement and modeling of self-heating in SOI nMOSFET's IEEE Transactions on Electron Devices ·L.T. Su,J.E. Chung,D.A. Antoniadis,Kenneth E. Goodson,M. I. Flik	1994	263
18	Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's IEEE Electron Device Letters ·L.T. Su,Daniel Dahlgren,J.E. Chung,D.A. Antoniadis	1994	77
19	Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's IEEE Electron Device Letters ·L.T. Su,Daniel Dahlgren,J.E. Chung,D.A. Antoniadis	1994	36
20	Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's IEEE Electron Device Letters ·L.T. Su,M. Sherony,María el Rocío Reyero Saavedra,J.E. Chung,D.A. Antoniadis	1994	12

About L.T. Su

L.T. Su is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Electronic, Optical and Magnetic Materials, Materials Chemistry and Biomedical Engineering, having authored 31 papers that have together received 1.1k indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (24 papers), Semiconductor materials and devices (24 papers), Silicon Carbide Semiconductor Technologies (12 papers), Integrated Circuits and Semiconductor Failure Analysis (5 papers), Low-power high-performance VLSI design (4 papers), Thermal properties of materials (3 papers), 3D IC and TSV technologies (3 papers) and Ferroelectric and Negative Capacitance Devices (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (944 citations), Electronic, Optical and Magnetic Materials (129 citations), Hardware and Architecture (37 citations), Materials Chemistry (225 citations) and Mechanics of Materials (67 citations). L.T. Su has collaborated with scholars based in United States, China and Germany. Frequent co-authors include D.A. Antoniadis, J.E. Chung, M. I. Flik, Kenneth E. Goodson, M. Sherony, R. Goldblatt, R. Schulz, R. Wachnik, Cyprian Uzoh and N. Lustig. Their work appears in journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, Journal of Heat Transfer, Applied Physics Letters and IEEE Journal of Solid-State Circuits.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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