J.E. Chung

2.6k citations

70 papers · 1.8k indexed · h-index 21

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
- Advancements in Photolithography Techniques

Papers in

Electrical and Electronic Engineering 67
- Semiconductor materials and devices 55
- Advancements in Semiconductor Devices and Circuit Design 53
- Integrated Circuits and Semiconductor Failure Analysis 22
- Ferroelectric and Negative Capacitance Devices 14
- Silicon Carbide Semiconductor Technologies 11
- Advancements in Photolithography Techniques 7
Hardware and Architecture 4
- VLSI and Analog Circuit Testing 4

Co-authors: Duane S. Boning D.A. Antoniadis L.T. Su B.E. Stine P.K. Ko M. I. Flik Kenneth E. Goodson Chenming Hu
Journals: IEEE Transactions on Electron Devices (14 papers)IEEE Electron Device Letters (8 papers)IEEE Transactions on Semiconductor Manufacturing (5 papers)IEEE Circuits and Devices Magazine (3 papers)IEEE Transactions on Nuclear Science (2 papers)
Partner nations: United States Germany Italy

In The Last Decade

J.E. Chung

63 papers receiving 1.7k citations

Peers

Countries citing papers authored by J.E. Chung

Since Specialization

Citations

This map shows the geographic impact of J.E. Chung's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J.E. Chung with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J.E. Chung more than expected).

Fields of papers citing papers by J.E. Chung

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J.E. Chung. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J.E. Chung. The network helps show where J.E. Chung may publish in the future.

Co-authors

The 25 scholars most cited alongside J.E. Chung, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J.E. Chung Line = papers co-authored together J.E. Chung links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Low-K Wire Bonding Rízia Tayline Nunes Silva, M. Normadiha, J.E. Chung, Kenta Hirose, Jin-Young Kim, S. S. Kim	2006	7
2	Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs J.E. Chung, M.-C. Jeng, J.E. Moon, P.K. Ko, C. Hu	2003	0
3	The effects of off-axis substrate orientation on MOSFET characteristics J.E. Chung, Anne Heitmann, M. E. Levi, P.K. Ko, C. Hu	2003	0
4	Optimization of series resistance in sub-0.2 μm SOI MOSFETs L.T. Su, M. Sherony, Hang Hu, J.E. Chung, D.A. Antoniadis	2002	11
5	Characteristics of submicrometer LOCOS isolation Ch. Karibuhoye, J.E. Chung, C.L. Keast	2002	0
6	Bias and variance in single and multiple response surface modeling T. Smith, Salman Talahmeh, Duane S. Boning, Jill Girardeau, J.E. Chung, Herbert H. Sawin	2002	2
7	A model for high-field conduction in SIMOX buried oxides Di Wang, Helen Niemeyer, 김외리, E F Meents, Junghyo Yoon, J.E. Chung	2002	2
8	Oxide-field dependence of the NMOS hot-carrier degradation rate and its impact on AC-lifetime prediction Samuel A. Oyeboade, Denis Žido, T.E. Kopley, J.E. Chung	2002	2
9	A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance B.E. Stine, Reinhold Bethke, Duane S. Boning, J.E. Chung, Людмил Илиев	2002	12
10	Improvement of breakdown voltage and off-state leakage in Ge-implanted SOI n-MOSFETs Mihai Emanuel Becica, Nader M. Kalkhoran, F. Namavar, J.E. Chung	2002	1
11	High-frequency AC hot-carrier degradation in CMOS circuits V. W. S. Chan, T.E. Kopley, Paul Marcoux, J.E. Chung	2002	6
12	Physics and technology of ultra short channel MOSFET devices D.A. Antoniadis, J.E. Chung	2002	14
13	The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes IEEE Transactions on Electron Devices ·B.E. Stine, Duane S. Boning, J.E. Chung, L.E. Camilletti, Roger Pradalié, Lawerence E. Williams, G. Walther, Lauren Duval, M. Muthukrishnan, Francisco Cabezuelo-Lorenzo, Michael R. Berman, 清志渡辺	1998	112
14	Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing IEEE Transactions on Semiconductor Manufacturing ·B.E. Stine, Dennis O. Ouma, Urban L. Throm, Duane S. Boning, J.E. Chung, Dale L. Hetherington, Stephanie A. Pink‐Harper, O.S. Nakagawa, Soo‐Young Oh	1998	90
15	Analysis and decomposition of spatial variation in integrated circuit processes and devices IEEE Transactions on Semiconductor Manufacturing ·B.E. Stine, Duane S. Boning, J.E. Chung	1997	172
16	Buried-oxide charge trapping induced performance degradation in fully-depleted ultra-thin SOI p-MOSFET's IEEE Transactions on Electron Devices ·Mihai Emanuel Becica, J.E. Chung, Nam Nguyễn	1996	7
17	A new algorithm for NMOS AC hot-carrier lifetime prediction based on the dominant degradation asymptote Noor Al-Sanjary, Denis Žido, J.E. Chung	1996	1
18	Measurement and modeling of self-heating in SOI nMOSFET's IEEE Transactions on Electron Devices ·L.T. Su, J.E. Chung, D.A. Antoniadis, Kenneth E. Goodson, M. I. Flik	1994	263
19	Parameter extraction guidelines for hot-electron reliability simulation Preeti Virdi, Imam Taufiqurrahman, J.E. Chung	1993	9
20	The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability IEEE Transactions on Electron Devices ·J.E. Chung, Anne Heitmann, P.K. Ko, C. Hu, M. E. Levi	1991	25

About J.E. Chung

J.E. Chung is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Industrial and Manufacturing Engineering, Biomedical Engineering and Electronic, Optical and Magnetic Materials, having authored 70 papers that have together received 1.8k indexed citations. Recurring topics across this work include Semiconductor materials and devices (55 papers), Advancements in Semiconductor Devices and Circuit Design (53 papers), Integrated Circuits and Semiconductor Failure Analysis (22 papers), Ferroelectric and Negative Capacitance Devices (14 papers), Silicon Carbide Semiconductor Technologies (11 papers), Advancements in Photolithography Techniques (7 papers), Advanced Surface Polishing Techniques (6 papers) and VLSI and Analog Circuit Testing (4 papers). The work is most often cited by research in Hardware and Architecture (232 citations), Electrical and Electronic Engineering (1.7k citations), Biomedical Engineering (331 citations), Industrial and Manufacturing Engineering (65 citations) and Statistics, Probability and Uncertainty (38 citations). J.E. Chung has collaborated with scholars based in United States, Germany and Italy. Frequent co-authors include Duane S. Boning, D.A. Antoniadis, L.T. Su, B.E. Stine, P.K. Ko, M. I. Flik, Kenneth E. Goodson, Chenming Hu, V. W. S. Chan and M.-C. Jeng. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Semiconductor Manufacturing, IEEE Circuits and Devices Magazine and IEEE Transactions on Nuclear Science.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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