W. Cote

794 citations

15 papers · 411 indexed · h-index 8

Impact in

Electronic, Optical and Magnetic Materials
- Copper Interconnects and Reliability
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Advancements in Semiconductor Devices and Circuit Design

Papers in ⓘ

Electrical and Electronic Engineering 13
- Semiconductor materials and devices 7
- Integrated Circuits and Semiconductor Failure Analysis 7
- 3D IC and TSV technologies 4
- Electronic Packaging and Soldering Technologies 3
- Advancements in Semiconductor Devices and Circuit Design 3
- VLSI and FPGA Design Techniques 2
Hardware and Architecture 5
- VLSI and Analog Circuit Testing 5

Co-authors: J. Heidenreich (2 shared papers)D. Edelstein (3 shared papers)A. Simon (2 shared papers)R. Goldblatt (2 shared papers)H. Rathore (2 shared papers)N. Lustig (2 shared papers)S. Luce (2 shared papers)P. Roper (1 shared paper)
Journals: Thin Solid Films (1 paper)IEEE Journal of Solid-State Circuits (1 paper)IEEE Transactions on Semiconductor Manufacturing (1 paper)IBM Journal of Research and Development (1 paper)
Partner nations: United States Switzerland

In The Last Decade

W. Cote

14 papers receiving 382 citations

Peers

Countries citing papers authored by W. Cote

Since Specialization

Citations

This map shows the geographic impact of W. Cote's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by W. Cote with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites W. Cote more than expected).

Fields of papers citing papers by W. Cote

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by W. Cote. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by W. Cote. The network helps show where W. Cote may publish in the future.

Co-authors

The 25 scholars most cited alongside W. Cote, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with W. Cote Line = papers co-authored together W. Cote links everyone, so they are left out of the graph.

All Works

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15 of 15 papers shown

#	Work
1	Full copper wiring in a sub-0.25 μm CMOS ULSI technology D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, Cyprian Uzoh, N. Lustig, P. Roper, T.L. McDevitt, W. Motsiff, A. Simon, John Dukovic, R. Wachnik, H. Rathore, R. Schulz, L.T. Su, S. Luce, John M. Slattery	2002	196
2	Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing Thin Solid Films ·Howard Landis, Peter J. Burke, W. Cote, William R. Hill, Cheryl Hoffman, Carter Kaanta, Charles W. Koburger, Walter Lange, Micheal Leach, S.L. Luce	1992	78
3	Dual Damascene: a ULSI wiring technology Carter Kaanta, S.G. Bombardier, W. Cote, William R. Hill, G. Kerszykowski, Howard Landis, D. Poindexter, C.W. Pollard, G.H. Ross, James G. Ryan, Sandra Wolff, J.E. Cronin	2002	36
4	Low-temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM IBM Journal of Research and Development ·D. Cote, S. Nguyen, W. Cote, S. Pennington, A. K. Stamper, D. V. Podlesnik	1995	26
5	Submicron wiring technology with tungsten and planarization Carter Kaanta, W. Cote, John Cronin, Karey Holland, Pei‐Ing Lee, Thomas P. Wright	1987	19
6	A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software M. P. Karthikeyan, Stephen R. Fox, W. Cote, Greg Yeric, Michael Hall, Joaquín Ignacio Bogado García, Braxton D. Mitchell, E. Wolf, Samarth Agarwal	2006	14
7	A 4-Mb low-temperature DRAM IEEE Journal of Solid-State Circuits ·W.H. Henkels, D.S. Wen, R. Mohler, R. Franch, T. Bucelot, Christopher Long, J.A. Bracchitta, W. Cote, G. Bronner, Y. Taur, R.H. Dennard	1991	13
8	A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software IEEE Transactions on Semiconductor Manufacturing ·Muthu Karthikeyan, Stephen R. Fox, W. Cote, Greg Yeric, Michael Hall, John Garcia, Barry Mitchell, Eric Wolf, Suresh Agarwal	2008	7
9	Submicron wiring technology with tungsten and planarization Carter Kaanta, W. Cote, John Cronin, Karey Holland, P.-I. Lee, Thomas P. Wright	2003	7
10	Short-flow test chip utilizing fast testing for defect density monitoring in 45nm Muthu Karthikeyan, W. Cote, Louis Medina, Ernesto Shiling, Arthur Gasasira, Amy Henning, William Ferrante, M. Craig, T. Merbeth	2008	5
11	Hyperspectral imaging using a Linear Variable Filter (LVF) based ultra-compact camera Thomas D. Rahmlow, W. Cote, Robert L. Johnson	2020	4
12	Copper dual damascene wiring for sub-0.25 μm CMOS technology J. Heidenreich, D. Edelstein, R. Goldblatt, W. Cote, Cyprian Uzoh, N. Lustig, T.L. McDevitt, Andrew Stamper, A. Simon, John Dukovic, P. C. Andricacos, R. Wachnik, H. Rathore, T. Katsetos, P. McLaughlin, S. Luce, John M. Slattery	2002	3
13	An evaluation of Cu wiring in a production 64 Mb DRAM W. Cote, G. Costrini, D. Edelstein, Christopher J. Osborn, D. Poindexter, V. Sardesai, G. Bronner	2002	2
14	Lithographically patterned fiber bundles for in-vivo Raman spectroscopy John B. Barton, Gary E. Carver, Sheetal Chanda, W. Cote, Sarah A. Locknar, Manish Gupta	2022	1
15	A buried-plate trench cell for a 64-Mb DRAM Donald P. Kenney, P. Parries, Paihung Pan, W. Tonti, W. Cote, S. Dash, Pierre Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, Wilfried Haensch, B. Hoffmann, M. Lévy, A.J. Yu, C. Zeller	2003	0

About W. Cote

W. Cote is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Electronic, Optical and Magnetic Materials, Biomedical Engineering and Computer Networks and Communications, having authored 15 papers that have together received 411 indexed citations. Recurring topics across this work include Semiconductor materials and devices (7 papers), Integrated Circuits and Semiconductor Failure Analysis (7 papers), Copper Interconnects and Reliability (5 papers), VLSI and Analog Circuit Testing (5 papers), 3D IC and TSV technologies (4 papers), Electronic Packaging and Soldering Technologies (3 papers), Advancements in Semiconductor Devices and Circuit Design (3 papers) and VLSI and FPGA Design Techniques (2 papers). The work is most often cited by research in Electronic, Optical and Magnetic Materials (170 citations), Electrical and Electronic Engineering (334 citations), Hardware and Architecture (31 citations), Biomedical Engineering (118 citations) and Mechanics of Materials (43 citations). W. Cote has collaborated with scholars based in United States and Switzerland. Frequent co-authors include J. Heidenreich, D. Edelstein, A. Simon, R. Goldblatt, H. Rathore, N. Lustig, S. Luce, P. Roper, John Dukovic and T.L. McDevitt. Their work appears in journals such as Thin Solid Films, IEEE Journal of Solid-State Circuits, IEEE Transactions on Semiconductor Manufacturing and IBM Journal of Research and Development.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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