Kimiyoshi Usami
About
In The Last Decade
Kimiyoshi Usami
94 papers receiving 1.5k citations
Peers
Comparison fields: 5 of 32
- Electrical and Electronic Engineering 1.4k
- Hardware and Architecture 777
- Computer Networks and Communications 391
- Biomedical Engineering 254
- Signal Processing 56
Countries citing papers authored by Kimiyoshi Usami
This map shows the geographic impact of Kimiyoshi Usami's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kimiyoshi Usami with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kimiyoshi Usami more than expected).
Fields of papers citing papers by Kimiyoshi Usami
This network shows the impact of papers produced by Kimiyoshi Usami. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kimiyoshi Usami. The network helps show where Kimiyoshi Usami may publish in the future.
Co-authorship network of co-authors of Kimiyoshi Usami
This figure shows the co-authorship network connecting the top 25 collaborators of Kimiyoshi Usami. A scholar is included among the top collaborators of Kimiyoshi Usami based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kimiyoshi Usami. Kimiyoshi Usami is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 1 | |
| 2 | 1 | |
| 3 | 1 | |
| 4 | 1 | |
| 5 | Circuit Structure of PUF using Leakage Current and Simulation Evaluation | 1 |
| 6 | Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing | 0 |
| 7 | 5 | |
| 8 | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data | 3 |
| 9 | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control | 2 |
| 10 | An MTJ-based Flip-Flop Circuit to Improve Robustness in Store/Restore Operations | 1 |
| 11 | Design and Evaluation of MTJ-based Standard Cell Memory | 0 |
| 12 | MTJ Based Non-Volatile Flip Flop to Prevent Useless Store Operation | 1 |
| 13 | Analytical model of energy dissipation for comparing adder architectures | 0 |
| 14 | 6 | |
| 15 | 11 | |
| 16 | 4 | |
| 17 | Temperature-dependent model for break-even time in fine-grain power gating and adaptive control based on the temperature dependence | 0 |
| 18 | Development of verification and power estimation methodology for circuits with Run Time Power Gating | 0 |
| 19 | 4 | |
| 20 | DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA. | 1 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.