Samuel Naffziger

3.1k total citations
55 papers, 2.2k citations indexed

About

Samuel Naffziger is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Samuel Naffziger has authored 55 papers receiving a total of 2.2k indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Electrical and Electronic Engineering, 35 papers in Hardware and Architecture and 11 papers in Computer Networks and Communications. Recurrent topics in Samuel Naffziger's work include Low-power high-performance VLSI design (33 papers), Parallel Computing and Optimization Techniques (27 papers) and Semiconductor materials and devices (14 papers). Samuel Naffziger is often cited by papers focused on Low-power high-performance VLSI design (33 papers), Parallel Computing and Optimization Techniques (27 papers) and Semiconductor materials and devices (14 papers). Samuel Naffziger collaborates with scholars based in United States, Canada and Germany. Samuel Naffziger's co-authors include T. Grutkowski, T. Chen, Mark Horowitz, E. Alon, Kevin M. Lepak, Barry M. Doyle, J. Desai, Blaine Stackhouse, Sean White and Ranjeet Kumar and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Micro.

In The Last Decade

Samuel Naffziger

55 papers receiving 2.1k citations

Peers

Countries citing papers authored by Samuel Naffziger

Since Specialization

Citations

This map shows the geographic impact of Samuel Naffziger's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Samuel Naffziger with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Samuel Naffziger more than expected).

Fields of papers citing papers by Samuel Naffziger

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Samuel Naffziger. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Samuel Naffziger. The network helps show where Samuel Naffziger may publish in the future.

Co-authorship network of co-authors of Samuel Naffziger

This figure shows the co-authorship network connecting the top 25 collaborators of Samuel Naffziger. A scholar is included among the top collaborators of Samuel Naffziger based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Samuel Naffziger. Samuel Naffziger is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product 2024 ·(unknown), Gabriel H. Loh, Michael Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, (unknown), (unknown), (unknown), Joseph L. Greathouse, (unknown), Raja Swaminathan	10
2	Coevolution of Chiplet Technology and Cache Architecture for AI and Compute 2024 ·John Wuu, Mike Mantor, Gabriel H. Loh, Alan Smith, Dave Johnson, David G. Fisher, Brett C. Johnson, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Deepak Kulkarni, (unknown), (unknown), Raja Swaminathan, Samuel Naffziger	2
3	AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization 2024 ·Alan Smith, Gabriel H. Loh, John Wuu, Samuel Naffziger, (unknown), (unknown), (unknown), (unknown), Raja Swaminathan	2
4	3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU 2022 ·2022 IEEE International Solid- State Circuits Conference (ISSCC) ·John Wuu, Rahul Agarwal, (unknown), (unknown), Brett C. Johnson, Dave Johnson, (unknown), Raja Swaminathan, (unknown), Samuel Naffziger	48
5	Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits 2021 ·Gabriel H. Loh, Samuel Naffziger, Kevin M. Lepak	22
6	2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products 2020 ·Samuel Naffziger, Kevin M. Lepak, (unknown), (unknown)	90
7	8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs 2020 ·(unknown), (unknown), (unknown), Samuel Naffziger, (unknown), (unknown), (unknown)	10
8	Multi-chip technologies to unleash computing performance gains over the next decade 2017 ·(unknown), Samuel Naffziger, (unknown)	50
9	Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU 2016 ·(unknown), (unknown), (unknown), (unknown), (unknown), Stephen Kosonocky, Samuel Naffziger	7
10	Resonant clock design for a power-efficient high-volume x86–64 microprocessor 2012 ·Visvesh Sathe, (unknown), (unknown), Marios C. Papaefthymiou, (unknown), Samuel Naffziger	7
11	Technology impacts from the new wave of architectures for media-rich workloads 2011 ·Symposium on VLSI Technology ·Samuel Naffziger	3
12	A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm<sup>2</sup> at 81% efficiency 2010 ·Hanh‐Phuc Le, Michael D. Seeman, Seth R. Sanders, Visvesh Sathe, Samuel Naffziger, Elad Alon	72
13	An x86-64 Core in 32 nm SOI CMOS 2010 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), Stephen Kosonocky, (unknown), (unknown), (unknown), Samuel Naffziger	20
14	Power and Temperature Control on a 90-nm Itanium Family Processor 2005 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), Jim Ignowski, (unknown), (unknown), Samuel Naffziger	230
15	Multi-Threaded Itanium®-Family Processor 2005 ·Samuel Naffziger, Blaine Stackhouse, T. Grutkowski	1
16	A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor 2005 ·IEEE Journal of Solid-State Circuits ·Tim Fischer, J. Desai, Barry M. Doyle, Samuel Naffziger, (unknown)	109
17	Clock distribution on a dual-core, multi-threaded Itanium/spl reg/ family microprocessor 2005 ·Barry M. Doyle, (unknown), E. Fetzer, Samuel Naffziger	6
18	Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation 2003 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·T. Chen, Samuel Naffziger	125
19	The implementation of the next-generation 64 b Itanium/sup TM/ microprocessor 2003 ·2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·Samuel Naffziger, Glenn Hammond	8
20	The implementation of the Itanium 2 microprocessor 2002 ·IEEE Journal of Solid-State Circuits ·Samuel Naffziger, (unknown), (unknown), (unknown), T. J. Sullivan, T. Grutkowski	139

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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