G. Dermer

1.1k total citations
20 papers, 862 citations indexed

About

G. Dermer is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Aerospace Engineering. According to data from OpenAlex, G. Dermer has authored 20 papers receiving a total of 862 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 10 papers in Hardware and Architecture and 5 papers in Aerospace Engineering. Recurrent topics in G. Dermer's work include Low-power high-performance VLSI design (8 papers), Semiconductor materials and devices (6 papers) and Satellite Communication Systems (5 papers). G. Dermer is often cited by papers focused on Low-power high-performance VLSI design (8 papers), Semiconductor materials and devices (6 papers) and Satellite Communication Systems (5 papers). G. Dermer collaborates with scholars based in United States. G. Dermer's co-authors include B. Bloechel, P. Hazucha, Tanay Karnik, Shekhar Borkar, S. Narendra, Vivek De, James Tschanz, Donald S. Gardner, G. Schrom and Jaehong Hahn and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, ACM SIGPLAN Notices and ACM SIGOPS Operating Systems Review.

In The Last Decade

G. Dermer

19 papers receiving 821 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
G. Dermer United States 12 751 310 164 143 24 20 862
Stephen Kosonocky United States 21 1.2k 1.6× 429 1.4× 231 1.4× 164 1.1× 9 0.4× 56 1.3k
Young-Hyun Jun South Korea 13 587 0.8× 111 0.4× 176 1.1× 129 0.9× 26 1.1× 60 667
Salvador Mir France 15 511 0.7× 348 1.1× 181 1.1× 54 0.4× 4 0.2× 68 586
V. Gutnik United States 7 414 0.6× 229 0.7× 163 1.0× 127 0.9× 13 0.5× 7 540
Eric Karl United States 19 843 1.1× 287 0.9× 39 0.2× 130 0.9× 6 0.3× 41 935
Michele Petracca United States 15 506 0.7× 212 0.7× 48 0.3× 282 2.0× 19 0.8× 32 699
Brian Curran Germany 13 358 0.5× 185 0.6× 37 0.2× 83 0.6× 8 0.3× 39 449
Stefan Rusu United States 15 808 1.1× 539 1.7× 78 0.5× 272 1.9× 3 0.1× 41 959
Umakanta Choudhury India 13 582 0.8× 364 1.2× 51 0.3× 41 0.3× 15 0.6× 32 633
Yiorgos Tsiatouhas Greece 11 603 0.8× 323 1.0× 85 0.5× 26 0.2× 3 0.1× 113 631

Countries citing papers authored by G. Dermer

Since Specialization
Citations

This map shows the geographic impact of G. Dermer's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by G. Dermer with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites G. Dermer more than expected).

Fields of papers citing papers by G. Dermer

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by G. Dermer. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by G. Dermer. The network helps show where G. Dermer may publish in the future.

Co-authorship network of co-authors of G. Dermer

This figure shows the co-authorship network connecting the top 25 collaborators of G. Dermer. A scholar is included among the top collaborators of G. Dermer based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with G. Dermer. G. Dermer is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Borkar, Nitin, Erik Seligman, Vasantha Erraguntla, et al.. (2005). 5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 2. 334–535. 1 indexed citations
2.
3.
Hazucha, P., G. Schrom, Jaehong Hahn, et al.. (2005). A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE Journal of Solid-State Circuits. 40(4). 838–845. 246 indexed citations
4.
5.
Schrom, G., P. Hazucha, Jaehong Hahn, et al.. (2004). A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control. 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551). 4702–4707. 82 indexed citations
6.
Hazucha, P., G. Schrom, Jaehong Hahn, et al.. (2004). A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS. 1. 256–257. 3 indexed citations
7.
Karnik, Tanay, James Tschanz, B. Bloechel, et al.. (2004). Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops. 324–325. 14 indexed citations
8.
Hazucha, P., Tanay Karnik, S.V. Walstra, et al.. (2004). Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. 617–620. 56 indexed citations
9.
Hazucha, P., Tanay Karnik, S.V. Walstra, et al.. (2004). Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process. IEEE Journal of Solid-State Circuits. 39(9). 1536–1543. 93 indexed citations
10.
Hazucha, P., Tanay Karnik, J. Maiz, et al.. (2004). Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation. 21.5.1–21.5.4. 118 indexed citations
11.
Narendra, S., James Tschanz, B. Bloechel, et al.. (2004). Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique. 156–518. 64 indexed citations
12.
Smith, James E., et al.. (2003). The Astronautics ZS-1 processor. 307–310. 3 indexed citations
13.
Hoskote, Yatin, B. Bloechel, G. Dermer, et al.. (2003). A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS. IEEE Journal of Solid-State Circuits. 38(11). 1866–1875. 30 indexed citations
14.
Narendra, S., Vasantha Erraguntla, H. Wilson, et al.. (2003). 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 270–466. 44 indexed citations
15.
Vangal, Sriram, Nitin Borkar, Erik Seligman, et al.. (2003). A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 412–478. 6 indexed citations
16.
17.
Smith, James E., et al.. (1987). The ZS-1 central processor. ACM SIGARCH Computer Architecture News. 15(5). 199–204. 61 indexed citations
18.
Smith, James E., et al.. (1987). The ZS-1 central processor. ACM SIGOPS Operating Systems Review. 21(4). 199–204. 1 indexed citations
19.
Smith, James E., et al.. (1987). The ZS-1 central processor. 199–204. 17 indexed citations
20.
Smith, James E., et al.. (1987). The ZS-1 central processor. ACM SIGPLAN Notices. 22(10). 199–204. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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