Tom Burd

2.5k citations

21 papers · 1.9k indexed · 2 hit papers · h-index 10

Impact in

Hardware and Architecture top 0.5%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Real-Time Systems Scheduling
Computer Networks and Communications top 2%
- Interconnection Networks and Systems

Papers in

Hardware and Architecture 12
- Parallel Computing and Optimization Techniques 9
- Embedded Systems Design Techniques 8
Electrical and Electronic Engineering 19
- Low-power high-performance VLSI design 14
- Semiconductor materials and devices 7
- Advancements in Semiconductor Devices and Circuit Design 3
- Advancements in PLL and VCO Technologies 2
- Radiation Effects in Electronics 2

Co-authors: R.W. Brodersen Trevor Pering Stephen Kosonocky Samuel Naffziger Miguel A. Rodríguez E. J. McLellan Dave Johnson Jonathan M. White
Journals: IEEE Journal of Solid-State Circuits (3 papers)
Partner nations: United States Canada

In The Last Decade

Tom Burd

18 papers receiving 1.7k citations

Hit Papers

align trajectories log scale

A dynamic voltage scaled microprocessor system 2000 · 663 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2000 IEEE Journal of Solid-State Circuits
1998 The simulation and evaluation of dynamic voltage scaling algorithms

Peers

Countries citing papers authored by Tom Burd

Since Specialization

Citations

This map shows the geographic impact of Tom Burd's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tom Burd with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tom Burd more than expected).

Fields of papers citing papers by Tom Burd

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tom Burd. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tom Burd. The network helps show where Tom Burd may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Tom Burd, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Tom Burd Line = papers co-authored together Tom Burd links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	“Zen 4”: The AMD 5nm 5.7GHz x86-64 Microprocessor Core Heather L. Brelje, Robert W. VanDine, Marina Rodrigues e Silva, A. A. Klimowicz, Brett C. Johnson, Lu Daqin, Djurre Broekhuis, Kevin Gillespie, Tom Burd, Harry D. Fair, David H. Johnson, Jonathan M. White, Y. Sergienko, Hou De-shun, Javin Olson, Wen-Gang Qi, Matthew D. Pickett, J. L. Castaño‐Almendral, Hien Nguyen, Angel Serafín Rodríguez de la Fuente	2023	19
2	Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads E. C. Ogden, Marsha Inanta Pulungan, Tom Burd, Ayse K. Coskun, John Kalamatianos	2023	6
3	Paradigm Shift in Semiconductor Technology Scaling Calling for Advancements in Design Modelling 浩行勝川, Girish Kini, Sriram Chandrasekaran, Sudhanva Gurumurthi, Viola Mp, Tom Burd	2023	2
4	4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management 咲子谷, Masaaki Ikawa, Stephen Kosonocky, M.K. Shmatikov, 千夏子眞榮城, Dilek Kandemir, Miguel A. Rodríguez, Tom Burd, I Vanea, Zachary Francis, Samuel Naffziger	2016	15
5	Bristol Ridge: A 28-nm $\times$ 86 Performance-Enhanced Microprocessor Through System Power Management IEEE Journal of Solid-State Circuits ·Masaaki Ikawa, 咲子谷, Samuel Naffziger, Tom Burd, Stephen Kosonocky, J Howland-Gradman, M.K. Shmatikov, Miguel A. Rodríguez, Zachary Francis, 千夏子眞榮城	2016	5
6	Carrizo: A High Performance, Energy Efficient 28 nm APU IEEE Journal of Solid-State Circuits ·Heather L. Brelje, Meriam Ellouzi, A A Zhakipova, Tom Burd, Craig Letner, J. Farrell, Dave Johnson, Kristina Vrotniakaite-Bajerciene, Dingzhou Liu, E. J. McLellan, Samuel Naffziger, Lu Daqin, Masaaki Ikawa, Jonathan White, 康人干川	2015	16
7	Designing in scaled technologies: 32 nm and beyond Stephen Kosonocky, Tom Burd, José Micael Delgado Barbosa, AJ Mellor, L Mouton	2012	7
8	Constraint Management and Checking in Template-Based Circuit Designs Cleandro de Albuquerque, Tom Burd, Brian R. McMinn, 脇田康章	2009	2
9	Context-sensitive static transistor-level IR analysis Weiqing Guo, Yu Lin Zhong, Tom Burd	2008	0
10	Context-sensitive static transistor-level IR analysis Weiqing Guo, Yu Lin Zhong, Tom Burd	2008	0
11	The simulation and evaluation of dynamic voltage scaling algorithms Trevor Pering, Tom Burd, R.W. Brodersen	2002	0
12	Design issues for Dynamic Voltage Scaling Tom Burd, R.W. Brodersen	2000	123
13	Voltage scheduling in the IpARM microprocessor system Trevor Pering, Tom Burd, R.W. Brodersen	2000	45
14	A dynamic voltage scaled microprocessor system Tom Burd, Trevor Pering, Bjarke A. K. Hübschmann, R.W. Brodersen	2000	141
15	A dynamic voltage scaled microprocessor system IEEE Journal of Solid-State Circuits ·Tom Burd, Trevor Pering, Bjarke A. K. Hübschmann, R.W. Brodersen Hit paper breakdown →	2000	663
16	Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System Trevor Pering, Tom Burd	1998	67
17	The simulation and evaluation of dynamic voltage scaling algorithms Trevor Pering, Tom Burd, R.W. Brodersen Hit paper breakdown →	1998	447
18	Energy efficient CMOS microprocessor design Tom Burd, R.W. Brodersen	1995	286
19	Design of wireless portable systems (unknown), Tom Burd, C. J., A. Deckmyn, Otoya Miyagi, Ken Lutz, Hafeez Awais, Trevor Pering, Brian Richards, Henry Alcántara Zanabria, Randy H. Katz, Jan M. Rabaey, R.W. Brodersen	1995	5
20	Research challenges in wireless multimedia R.W. Brodersen, Tom Burd, C. J., A. Deckmyn, Anantha P. Chandrakasan, Otoya Miyagi, Ulrich Bogdahn, Trevor Pering, Brian Richards, Henry Alcántara Zanabria, Jan M. Rabaey	1994	6

About Tom Burd

Tom Burd is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Vision and Pattern Recognition, Signal Processing and Computer Networks and Communications, having authored 21 papers that have together received 1.9k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (14 papers), Parallel Computing and Optimization Techniques (9 papers), Embedded Systems Design Techniques (8 papers), Semiconductor materials and devices (7 papers), Advancements in Semiconductor Devices and Circuit Design (3 papers), Advancements in PLL and VCO Technologies (2 papers), Interconnection Networks and Systems (2 papers) and Radiation Effects in Electronics (2 papers). The work is most often cited by research in Hardware and Architecture (1.1k citations), Computer Networks and Communications (627 citations), Electrical and Electronic Engineering (1.1k citations), Information Systems (177 citations) and Biomedical Engineering (241 citations). Tom Burd has collaborated with scholars based in United States and Canada. Frequent co-authors include R.W. Brodersen, Trevor Pering, Stephen Kosonocky, Samuel Naffziger, Miguel A. Rodríguez, E. J. McLellan, Dave Johnson, Jonathan M. White, John Kalamatianos and David H. Johnson. Their work appears in journals such as IEEE Journal of Solid-State Circuits.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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