S. Sathaye

667 total citations
21 papers, 449 citations indexed

About

S. Sathaye is a scholar working on Hardware and Architecture, Computer Networks and Communications and Artificial Intelligence. According to data from OpenAlex, S. Sathaye has authored 21 papers receiving a total of 449 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Hardware and Architecture, 11 papers in Computer Networks and Communications and 4 papers in Artificial Intelligence. Recurrent topics in S. Sathaye's work include Parallel Computing and Optimization Techniques (20 papers), Embedded Systems Design Techniques (12 papers) and Interconnection Networks and Systems (5 papers). S. Sathaye is often cited by papers focused on Parallel Computing and Optimization Techniques (20 papers), Embedded Systems Design Techniques (12 papers) and Interconnection Networks and Systems (5 papers). S. Sathaye collaborates with scholars based in United States. S. Sathaye's co-authors include Erik Altman, Michael Gschwind, Kemal Ebci̇oğlu, Thomas M. Conte, Kishore N. Menezes, Sanjeev Banerjia, A. A. Bright, Stephen Kosonocky, Jason E. Fritts and Matthew Jennings and has published in prestigious journals such as Proceedings of the IEEE, Computer and IEEE Transactions on Computers.

In The Last Decade

S. Sathaye

20 papers receiving 397 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S. Sathaye United States 11 420 292 105 49 47 21 449
Kishore N. Menezes United States 11 457 1.1× 322 1.1× 149 1.4× 54 1.1× 50 1.1× 15 490
Lisa Spainhower United States 8 233 0.6× 232 0.8× 282 2.7× 62 1.3× 62 1.3× 14 411
Christopher B. Colohan United States 8 662 1.6× 606 2.1× 57 0.5× 57 1.2× 67 1.4× 18 690
David W. L. Yen United States 5 358 0.9× 255 0.9× 56 0.5× 37 0.8× 23 0.5× 10 391
Michael D. Smith United States 7 292 0.7× 230 0.8× 51 0.5× 62 1.3× 75 1.6× 12 338
Jordi Tubella Spain 10 312 0.7× 275 0.9× 82 0.8× 55 1.1× 61 1.3× 28 397
Yanos Sazeides Cyprus 8 383 0.9× 300 1.0× 156 1.5× 43 0.9× 49 1.0× 14 421
Wonsun Ahn United States 8 247 0.6× 229 0.8× 30 0.3× 48 1.0× 48 1.0× 14 295
John H. Kelm United States 10 347 0.8× 322 1.1× 95 0.9× 23 0.5× 32 0.7× 20 378
Pedro Marcuello Spain 11 579 1.4× 517 1.8× 66 0.6× 35 0.7× 50 1.1× 23 610

Countries citing papers authored by S. Sathaye

Since Specialization
Citations

This map shows the geographic impact of S. Sathaye's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Sathaye with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Sathaye more than expected).

Fields of papers citing papers by S. Sathaye

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Sathaye. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Sathaye. The network helps show where S. Sathaye may publish in the future.

Co-authorship network of co-authors of S. Sathaye

This figure shows the co-authorship network connecting the top 25 collaborators of S. Sathaye. A scholar is included among the top collaborators of S. Sathaye based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Sathaye. S. Sathaye is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Ebci̇oğlu, Kemal, Erik Altman, S. Sathaye, & Michael Gschwind. (2003). Optimizations and oracle parallelism with dynamic translation. 284–295. 3 indexed citations
2.
3.
Conte, Thomas M., Kishore N. Menezes, & S. Sathaye. (2002). A technique to determine power-efficient, high-performance superscalar processors. 220. 324–333. 6 indexed citations
4.
Altman, Erik, Kemal Ebci̇oğlu, Michael Gschwind, & S. Sathaye. (2001). Advances and future challenges in binary translation and optimization. Proceedings of the IEEE. 89(11). 1710–1722. 22 indexed citations
5.
Ebci̇oğlu, Kemal, Erik Altman, Michael Gschwind, & S. Sathaye. (2001). Dynamic binary translation and optimization. IEEE Transactions on Computers. 50(6). 529–548. 103 indexed citations
6.
Conte, Thomas M., et al.. (2000). System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8(2). 129–137. 30 indexed citations
7.
Altman, Erik, Michael Gschwind, S. Sathaye, et al.. (2000). BOA: The Architecture of a Binary Translation Processor. 31 indexed citations
8.
Gschwind, Michael, Kemal Ebci̇oğlu, Erik Altman, & S. Sathaye. (2000). Binary translation and architecture convergence issues for IBM system/390. 336–347. 9 indexed citations
9.
Conte, Thomas M. & S. Sathaye. (2000). Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility. IEEE Transactions on Computers. 49(8). 814–825. 4 indexed citations
10.
Gschwind, Michael, et al.. (2000). Dynamic and transparent binary translation. Computer. 33(3). 54–59. 85 indexed citations
11.
Sathaye, S., Stephen Kosonocky, Michael Gschwind, et al.. (1999). BOA: Targeting Multi-Gigahertz with Binary Translation. 20 indexed citations
12.
Ebci̇oğlu, Kemal, Erik Altman, Michael Gschwind, & S. Sathaye. (1999). Optimizations and oracle parallelism with dynamic translation. International Symposium on Microarchitecture. 284–295. 23 indexed citations
13.
Altman, Erik, Michael Gschwind, S. Sathaye, et al.. (1999). IBM Research Report BOA: The Architecture of a Binary Translation Processor. 3 indexed citations
14.
Özer, Emre, S. Sathaye, Kishore N. Menezes, et al.. (1998). A fast interrupt handling scheme for VLIW processors. International Conference on Parallel Architectures and Compilation Techniques. 136–141. 8 indexed citations
15.
Banerjia, Sanjeev, S. Sathaye, Kishore N. Menezes, & Thomas M. Conte. (1998). MPS: miss-path scheduling for multiple-issue processors. IEEE Transactions on Computers. 47(12). 1382–1397. 11 indexed citations
16.
Menezes, Kishore N., et al.. (1997). Path prediction for high issue-rate processors. International Conference on Parallel Architectures and Compilation Techniques. 178–188. 7 indexed citations
17.
Conte, Thomas M. & S. Sathaye. (1997). Optimization of VLIW compatibility systems employing dynamic rescheduling. International Journal of Parallel Programming. 25(2). 83–112. 5 indexed citations
18.
Conte, Thomas M., S. Sathaye, & Sanjeev Banerjia. (1996). A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures. International Symposium on Microarchitecture. 4–13. 6 indexed citations
19.
Conte, Thomas M., et al.. (1996). Instruction fetch mechanisms for VLIW architectures with compressed encodings. International Symposium on Microarchitecture. 201–211. 40 indexed citations
20.
Conte, Thomas M. & S. Sathaye. (1995). Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. 208–218. 14 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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