Jim Tschanz

2.2k total citations · 1 hit paper
26 papers, 1.6k citations indexed

About

Jim Tschanz is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Jim Tschanz has authored 26 papers receiving a total of 1.6k indexed citations (citations by other indexed papers that have themselves been cited), including 25 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 3 papers in Computer Networks and Communications. Recurrent topics in Jim Tschanz's work include Low-power high-performance VLSI design (19 papers), Semiconductor materials and devices (13 papers) and Advancements in Semiconductor Devices and Circuit Design (12 papers). Jim Tschanz is often cited by papers focused on Low-power high-performance VLSI design (19 papers), Semiconductor materials and devices (13 papers) and Advancements in Semiconductor Devices and Circuit Design (12 papers). Jim Tschanz collaborates with scholars based in United States, Switzerland and India. Jim Tschanz's co-authors include Vivek De, S. Narendra, Shekhar Borkar, Tanay Karnik, A. Keshavarzi, Keith Bowman, R. Nair, Muhammad Khellah, Jaydeep P. Kulkarni and Bibiche Geuskens and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

In The Last Decade

Jim Tschanz

25 papers receiving 1.5k citations

Hit Papers

Parameter variations and impact on circuits and microarch... 2003 2026 2010 2018 2003 250 500 750 1000
What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

  1. Parameter variations and impact on circuits and microarchitecture
    2003 1.1k citations Shekhar Borkar, Tanay Karnik et al. profile →

Peers

Jim Tschanz
Keith Bowman United States
Muhammad Khellah United States
E. Alon United States
Kimiyoshi Usami Japan
Koji Nii Japan
Stefan Rusu United States
Ik‐Joon Chang South Korea
Toan Thang Pham United States
Tim Tuan United States
Robert M. Senger United States
Keith Bowman United States
Jim Tschanz
Citations per year, relative to Jim Tschanz Jim Tschanz (= 1×) peers Keith Bowman

Countries citing papers authored by Jim Tschanz

Since Specialization
Citations

This map shows the geographic impact of Jim Tschanz's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jim Tschanz with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jim Tschanz more than expected).

Fields of papers citing papers by Jim Tschanz

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jim Tschanz. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jim Tschanz. The network helps show where Jim Tschanz may publish in the future.

Co-authorship network of co-authors of Jim Tschanz

This figure shows the co-authorship network connecting the top 25 collaborators of Jim Tschanz. A scholar is included among the top collaborators of Jim Tschanz based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jim Tschanz. Jim Tschanz is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Krishnamurthy, Harish K., Kaladhar Radhakrishnan, Vivek De, et al.. (2024). A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control. 1–2.
2.
Pellerano, Stefano, et al.. (2022). Innovations for Intelligent Edge. 41–44. 2 indexed citations
3.
Paul, Somnath, Charles Augustine, Raghavan Kumar, et al.. (2020). A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. 1–2. 5 indexed citations
4.
Krishnamurthy, Harish K., Vaibhav Vaidya, Sheldon Weng, et al.. (2017). 20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. 336–337. 32 indexed citations
5.
Chen, Chia‐Hsiang, Keith Bowman, Charles Augustine, Zhengya Zhang, & Jim Tschanz. (2013). Minimum supply voltage for sequential logic circuits in a 22nm technology. 181–186. 5 indexed citations
6.
Jain, Rinkle, Bibiche Geuskens, Muhammad Khellah, et al.. (2013). A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS. 2013. 145–146. 26 indexed citations
7.
Kulkarni, Jaydeep P., Muhammad Khellah, Jim Tschanz, et al.. (2013). Dual-V CC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range. 15 indexed citations
8.
Chen, Chia‐Hsiang, Keith Bowman, Charles Augustine, Zhengya Zhang, & Jim Tschanz. (2013). Minimum supply voltage for sequential logic circuits in a 22nm technology. 181–186. 5 indexed citations
9.
Nicolaidis, M., Lorena Anghel, Y. Zorian, et al.. (2012). Design for test and reliability in ultimate CMOS. 27. 677–682. 5 indexed citations
10.
Bowman, Keith, Carlos Tokunaga, Tanay Karnik, Vivek De, & Jim Tschanz. (2012). A 22nm dynamically adaptive clock distribution for voltage droop tolerance. 94–95. 13 indexed citations
11.
Raychowdhury, Arijit, Jim Tschanz, Keith Bowman, et al.. (2011). Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 1(3). 208–217. 7 indexed citations
12.
Raychowdhury, Arijit, Bibiche Geuskens, Jaydeep P. Kulkarni, et al.. (2010). PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. 352–353. 43 indexed citations
13.
Zhang, Ming, et al.. (2007). Design for Resilience to Soft Errors and Variations. 23–28. 16 indexed citations
14.
Ghoneima, Maged, Yehea Ismail, Muhammad Khellah, Jim Tschanz, & Vivek De. (2006). Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications. 53(9). 1928–1933. 15 indexed citations
15.
Ghoneima, Maged, Yehea Ismail, Muhammad Khellah, Jim Tschanz, & Vivek De. (2006). Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(5). 821–836. 30 indexed citations
16.
Tschanz, Jim, Keith Bowman, & Vivek De. (2005). Variation-tolerant circuits. 762–762. 49 indexed citations
17.
Tschanz, Jim, S. Narendra, R. Nair, & Vivek De. (2003). Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. IEEE Journal of Solid-State Circuits. 38(5). 826–829. 97 indexed citations
18.
Borkar, Shekhar, Tanay Karnik, S. Narendra, et al.. (2003). Parameter variations and impact on circuits and microarchitecture. 338–342. 1062 indexed citations breakdown →
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Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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