S.A. Hareland

1.8k citations

32 papers · 1.3k indexed · h-index 15

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing 3
Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices 27
- Advancements in Semiconductor Devices and Circuit Design 23
- Integrated Circuits and Semiconductor Failure Analysis 6
- Radiation Effects in Electronics 6
- Silicon Carbide Semiconductor Technologies 5
Atomic and Molecular Physics, and Optics
- Quantum and electron transport phenomena 6
Biomedical Engineering
Software
Medical Laboratory Technology
- Quality and Safety in Healthcare 3

Co-authors: J. Maiz Peter R. Armstrong R. Chau M. Doczy Suman Datta B. Jin J. Kavalieros A.F. Tasch
Cited by: Hardware and Architecture Electrical and Electronic Engineering Atomic and Molecular Physics, and Optics
Journals: IEEE Transactions on Electron Devices (8 papers)IEEE Electron Device Letters (3 papers)Electronics Letters (1 paper)
Partner nations: United States United Kingdom

In The Last Decade

S.A. Hareland

28 papers receiving 1.2k citations

Peers

Countries citing papers authored by S.A. Hareland

Since Specialization

Citations

This map shows the geographic impact of S.A. Hareland's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S.A. Hareland with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S.A. Hareland more than expected).

Fields of papers citing papers by S.A. Hareland

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S.A. Hareland. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S.A. Hareland. The network helps show where S.A. Hareland may publish in the future.

Co-authorship network

The 25 scholars most cited alongside S.A. Hareland, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S.A. Hareland Line = papers co-authored together S.A. Hareland links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Practical aspects of building a constrained random test framework for safety-critical embedded systems Thiago Henrique Melo Silva,Isaac Amundson,S.A. Hareland,Sanjai Rayadurgam	2014	2
2	Prognostic opportunities and limitations in implantable medical devices S.A. Hareland,カイチサイトウ	2013	0
3	Reliability considerations for implantable medical ICs Anne L. Fairbairn,Bellis,隆規角田,O. Schwab,R. Hamprecht,Anastasiia Gotgelf,Antonius Yansen Suryadarma,S.A. Hareland	2008	9
4	Characterization of multi-bit soft error events in advanced SRAMs J. Maiz,S.A. Hareland,Kedong Zhang,Peter R. Armstrong	2004	186
5	Ultra high speed, very low power InSbb-based quantum well FETs for logic applications Sarah P. Ho,Dimitra Kentroti,Andrew M. Bogatkevich,阿南健二,M. T. Emeny,Xiao Juan Liu,S.A. Hareland,L. Haworth,D.G. Hayes,K.P. Hilton,Richard Jefferies,Trevor Martin,K. J. Nash,T. J. Phillips,William Milligan,R. Chau	2004	3
6	Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout Barry M. Doyle,B. I. Boyanov,Suman Datta,M. Doczy,S.A. Hareland,B. Jin,J. Kavalieros,T. Linton,R. Rios,R. Chau	2004	163
7	Silicon nano-transistors and breaking the 10 nm physical gate length barrier R. Chau,Barry M. Doyle,M. Doczy,Suman Datta,S.A. Hareland,B. Jin,J. Kavalieros,M. Metz	2004	35
8	High performance fully-depleted tri-gate CMOS transistors IEEE Electron Device Letters ·B.S. Doyle,Suman Datta,M. Doczy,S.A. Hareland,B. Jin,J. Kavalieros,T. Linton,A. Murthy,R. Rios,R. Chau	2003	324
9	An accurate preprocessor for Monte Carlo study of electron transport in inversion layers of silicon nMOSFETs Syamala Diwakaruni,S.A. Hareland,S. Jallepalli,C.M. Maziar,A.F. Tasch	2002	0
10	Impact of CMOS process scaling and SOI on the soft error rates of logic processes S.A. Hareland,J. Maiz,M. Alavi,K. Mistry,W. Hazeu,Changhong Dai	2002	93
11	An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si IEEE Transactions on Electron Devices ·G. Chindalore,W.-K. Shih,S. Jallepalli,S.A. Hareland,A.F. Tasch,C.M. Maziar	2000	6
12	Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMOS technology Changhong Dai,照英,S.A. Hareland,J. Maiz,Ariane Girard	1999	12
13	A physically-based model for quantization effects in hole inversion layers IEEE Transactions on Electron Devices ·S.A. Hareland,S. Jallepalli,Jing Geng,Haihong Wang,G. Chindalore,A.F. Tasch,C.M. Maziar	1998	13
14	An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers IEEE Transactions on Electron Devices ·G. Chindalore,Abdulla Alakour,S. Mudanai,S.A. Hareland,W.-K. Shih,Ma Teresa Román Pérez,A.F. Tasch,C.M. Maziar	1998	9
15	Computationally efficient models for quantization effects in MOS electron and hole accumulation layers IEEE Transactions on Electron Devices ·S.A. Hareland,宣学章,W.-K. Shih,S. Jallepalli,Yuanyuan Yu,G. Chindalore,A.F. Tasch,C.M. Maziar	1998	27
16	Experimental determination of electron and hole mobilities in MOS accumulation layers IEEE Electron Device Letters ·Abdulla Alakour,G. Chindalore,S.A. Hareland,W.-K. Shih,C. Wang,A.F. Tasch,C.M. Maziar	1997	14
17	A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS devices IEEE Transactions on Electron Devices ·S.A. Hareland,S. Jallepalli,G. Chindalore,W.-K. Shih,A.F. Tasch,Jacinta Bitonye	1997	17
18	Manufacturing sensitivity analysis of a 0.18-micron NMOSFET Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Nurrus Sa'adah,S.A. Hareland,Minni Tapola,Zhen Kai Wan,A.F. Tasch,P. Zeitzoff	1996	2
19	A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's IEEE Transactions on Electron Devices ·Zhen Kai Wan,M. Carrington,S. Jallepalli,W.-K. Shih,S.A. Hareland,E. Skrzydlewska,A.F. Tasch,C.M. Maziar	1996	55
20	New structural approach for reducing punchthrough current in deep submicrometre MOSFETs and extending MOSFET scaling Electronics Letters ·S.A. Hareland,A.F. Tasch,C.M. Maziar	1993	21

About S.A. Hareland

S.A. Hareland is a scholar working on Medical Laboratory Technology, Electrical and Electronic Engineering, Hardware and Architecture, Software and Atomic and Molecular Physics, and Optics, having authored 32 papers that have together received 1.3k indexed citations. Recurring topics across this work include Semiconductor materials and devices (27 papers), Advancements in Semiconductor Devices and Circuit Design (23 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Radiation Effects in Electronics (6 papers), Quantum and electron transport phenomena (6 papers), Silicon Carbide Semiconductor Technologies (5 papers), Quality and Safety in Healthcare (3 papers) and VLSI and Analog Circuit Testing (3 papers). The work is most often cited by research in Hardware and Architecture (255 citations), Electrical and Electronic Engineering (1.3k citations), Atomic and Molecular Physics, and Optics (143 citations), Biomedical Engineering (197 citations) and Software (14 citations). S.A. Hareland has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include J. Maiz, Peter R. Armstrong, R. Chau, M. Doczy, Suman Datta, B. Jin, J. Kavalieros, A.F. Tasch, R. Rios and T. Linton. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Electronics Letters, IEEE Transactions on Device and Materials Reliability and VLSI design.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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