Yung-Fa Chou

837 total citations
63 papers, 641 citations indexed

About

Yung-Fa Chou is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Yung-Fa Chou has authored 63 papers receiving a total of 641 indexed citations (citations by other indexed papers that have themselves been cited), including 62 papers in Electrical and Electronic Engineering, 34 papers in Hardware and Architecture and 10 papers in Biomedical Engineering. Recurrent topics in Yung-Fa Chou's work include 3D IC and TSV technologies (31 papers), VLSI and Analog Circuit Testing (30 papers) and Integrated Circuits and Semiconductor Failure Analysis (25 papers). Yung-Fa Chou is often cited by papers focused on 3D IC and TSV technologies (31 papers), VLSI and Analog Circuit Testing (30 papers) and Integrated Circuits and Semiconductor Failure Analysis (25 papers). Yung-Fa Chou collaborates with scholars based in Taiwan, United States and United Kingdom. Yung-Fa Chou's co-authors include Ding-Ming Kwai, Cheng‐Wen Wu, Shi‐Yu Huang, Kuo-Liang Cheng, Jin-Fu Li, Jen-Chieh Yeh, Chih-Tsun Huang, Wu-Tung Cheng, Kun-Han Tsai and Stephen Sunter and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Yung-Fa Chou

61 papers receiving 615 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Yung-Fa Chou Taiwan	14	602	290	83	76	38	63	641
G. Dermer United States	12	751 1.2×	310 1.1×	143 1.7×	164 2.2×	24 0.6×	20	862
Umakanta Choudhury India	13	582 1.0×	364 1.3×	41 0.5×	51 0.7×	15 0.4×	32	633
Ding-Ming Kwai Taiwan	16	898 1.5×	397 1.4×	222 2.7×	132 1.7×	60 1.6×	97	1.0k
Young-Hyun Jun South Korea	13	587 1.0×	111 0.4×	129 1.6×	176 2.3×	26 0.7×	60	667
Alan J. Drake United States	11	570 0.9×	321 1.1×	101 1.2×	93 1.2×	5 0.1×	26	662
Shreepad Panth United States	13	597 1.0×	151 0.5×	161 1.9×	21 0.3×	36 0.9×	29	642
Hyung-Taek Lim Germany	10	154 0.3×	168 0.6×	240 2.9×	44 0.6×	18 0.5×	23	339
Bill Eklow United States	12	432 0.7×	235 0.8×	77 0.9×	26 0.3×	85 2.2×	28	492
Brian Curran Germany	13	358 0.6×	185 0.6×	83 1.0×	37 0.5×	8 0.2×	39	449
Michele Petracca United States	15	506 0.8×	212 0.7×	282 3.4×	48 0.6×	19 0.5×	32	699

Countries citing papers authored by Yung-Fa Chou

Since Specialization

Citations

This map shows the geographic impact of Yung-Fa Chou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yung-Fa Chou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yung-Fa Chou more than expected).

Fields of papers citing papers by Yung-Fa Chou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yung-Fa Chou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yung-Fa Chou. The network helps show where Yung-Fa Chou may publish in the future.

Co-authorship network of co-authors of Yung-Fa Chou

This figure shows the co-authorship network connecting the top 25 collaborators of Yung-Fa Chou. A scholar is included among the top collaborators of Yung-Fa Chou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yung-Fa Chou. Yung-Fa Chou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

1.

Huang, Shi‐Yu, et al.. (2020). Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Design and Test. 37(4). 101–107. 6 indexed citations

2.

Shen, Wen-Wei, Ming‐Jer Kao, Kuan‐Neng Chen, et al.. (2018). 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV). IEEE Journal of the Electron Devices Society. 6. 396–402. 11 indexed citations

3.

Li, Jin-Fu, et al.. (2018). A channel-sharable built-in self-test scheme for multi-channel DRAMs. Asia and South Pacific Design Automation Conference. 245–250. 1 indexed citations

4.

Li, Jin-Fu, et al.. (2016). A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. 1–7. 13 indexed citations

5.

Lin, Tzu‐Ying, et al.. (2016). A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. 281–286. 2 indexed citations

6.

Huang, Shi‐Yu, et al.. (2015). Testing power-delivery TSVs. 127–131. 3 indexed citations

7.

Kwai, Ding-Ming, et al.. (2013). Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(2). 207–219. 4 indexed citations

8.

Kwai, Ding-Ming, et al.. (2013). An FPGA-based test platform for analyzing data retention time distribution of DRAMs. 1–4. 15 indexed citations

9.

Yu, Hao, et al.. (2012). Thermal stress aware design for stacking IC with through glass via. 133–136. 3 indexed citations

10.

Huang, Jiun-Lang, et al.. (2011). A self-testing and calibration method for embedded successive approximation register ADC. Asia and South Pacific Design Automation Conference. 713–718. 7 indexed citations

11.

Huang, Jiun-Lang, et al.. (2011). On Pre/Post-Bond Testing and Calibrating SAR ADC Array in 3-D CMOS Imager. 25–28. 1 indexed citations

12.

Lin, Ta‐Wei, Kun‐Ju Tsai, Yung-Fa Chou, et al.. (2011). Design and implementation of 3D-thermal test chip for exploration of package effects. 238–241. 2 indexed citations

13.

Kwai, Ding-Ming, et al.. (2010). CAD reference flow for 3D via-last integrated circuits. Asia and South Pacific Design Automation Conference. 187–192. 6 indexed citations

14.

Huang, Shi‐Yu, et al.. (2010). Performance Characterization of TSV in 3D IC via Sensitivity Analysis. 389–394. 52 indexed citations

15.

Li, Jin-Fu, et al.. (2010). A Test Integration Methodology for 3D Integrated Circuits. 377–382. 24 indexed citations

16.

Huang, Rei-Fu, et al.. (2004). SRAM delay fault modeling and test algorithm development. Asia and South Pacific Design Automation Conference. 104–109. 2 indexed citations

17.

Cheng, Kuo-Liang, et al.. (2004). Fault pattern oriented defect diagnosis for memories. 1. 29–38. 16 indexed citations

18.

Huang, Rei-Fu, et al.. (2004). SRAM delay fault modeling and test algorithm development. 104–109. 2 indexed citations

19.

Cheng, Kuo-Liang, et al.. (2003). FAME: A Fault-Pattern Based Memory Failure Analysis Framework. International Conference on Computer Aided Design. 595–598. 8 indexed citations

20.

Huang, Rei-Fu, Yung-Fa Chou, & Cheng‐Wen Wu. (2003). Defect oriented fault analysis for SRAM. 256–261. 17 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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