Wu-Tung Cheng
- Electrical and Electronic Engineering top 1%
- Hardware and Architecture top 0.1%
- Control and Systems Engineering top 5%
- Industrial and Manufacturing Engineering top 5%
- Computer Networks and Communications top 10%
- Co-authors
- Yu HuangS.M. ReddyJ.H. PatelT.M. NiermannKun-Han TsaiNilanjan MukherjeeT.J. ChakrabortyRuifeng Guo
- Topics
- VLSI and Analog Circuit Testing (156 papers)Integrated Circuits and Semiconductor Failure Analysis (145 papers)Advancements in Photolithography Techniques (26 papers)
- Partner nations
- United StatesHungaryTaiwan
In The Last Decade
Wu-Tung Cheng
171 papers receiving 2.8k citations
Peers
Comparison fields: 5 of 35
- Electrical and Electronic Engineering 2.8k
- Hardware and Architecture 2.7k
- Control and Systems Engineering 232
- Industrial and Manufacturing Engineering 155
- Computer Networks and Communications 123
Countries citing papers authored by Wu-Tung Cheng
This map shows the geographic impact of Wu-Tung Cheng's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Wu-Tung Cheng with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Wu-Tung Cheng more than expected).
Fields of papers citing papers by Wu-Tung Cheng
This network shows the impact of papers produced by Wu-Tung Cheng. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Wu-Tung Cheng. The network helps show where Wu-Tung Cheng may publish in the future.
Co-authorship network of co-authors of Wu-Tung Cheng
This figure shows the co-authorship network connecting the top 25 collaborators of Wu-Tung Cheng. A scholar is included among the top collaborators of Wu-Tung Cheng based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Wu-Tung Cheng. Wu-Tung Cheng is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 5 | |
| 2 | 6 | |
| 3 | 3 | |
| 4 | 0 | |
| 5 | 15 | |
| 6 | 16 | |
| 7 | 7 | |
| 8 | 4 | |
| 9 | 9 | |
| 10 | 13 | |
| 11 | 24 | |
| 12 | 15 | |
| 13 | 3 | |
| 14 | 37 | |
| 15 | 18 | |
| 16 | 24 | |
| 17 | 6 | |
| 18 | The Pitfalls of Necessary Assignments | 1 |
| 19 | 23 | |
| 20 | Multiple-Fault Detection in Iterative Logic Arrays. | 7 |
About Wu-Tung Cheng
Wu-Tung Cheng is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Industrial and Manufacturing Engineering, having authored 182 papers that have together received 3.0k indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (156 papers), Integrated Circuits and Semiconductor Failure Analysis (145 papers) and Advancements in Photolithography Techniques (26 papers). The work is most often cited by research in Hardware and Architecture (2.7k citations), Electrical and Electronic Engineering (2.8k citations) and Software (119 citations). Wu-Tung Cheng has collaborated with scholars based in United States, Hungary and Taiwan. Frequent co-authors include Yu Huang, S.M. Reddy, J.H. Patel, T.M. Niermann, Kun-Han Tsai, Nilanjan Mukherjee, T.J. Chakraborty, Ruifeng Guo, Shi‐Yu Huang and Janusz Rajski. Their work appears in journals such as IEEE Journal of Solid-State Circuits, Computer and IEEE Transactions on Computers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.