Shih-Chieh Chang

1.4k total citations
55 papers, 670 citations indexed

About

Shih-Chieh Chang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Shih-Chieh Chang has authored 55 papers receiving a total of 670 indexed citations (citations by other indexed papers that have themselves been cited), including 46 papers in Electrical and Electronic Engineering, 32 papers in Hardware and Architecture and 15 papers in Computer Networks and Communications. Recurrent topics in Shih-Chieh Chang's work include Low-power high-performance VLSI design (27 papers), VLSI and Analog Circuit Testing (13 papers) and VLSI and FPGA Design Techniques (11 papers). Shih-Chieh Chang is often cited by papers focused on Low-power high-performance VLSI design (27 papers), VLSI and Analog Circuit Testing (13 papers) and VLSI and FPGA Design Techniques (11 papers). Shih-Chieh Chang collaborates with scholars based in Taiwan, United States and China. Shih-Chieh Chang's co-authors include Cheng-Hung Lin, Chih-Tsun Huang, Malgorzata Marek-Sadowska, Cheng-Hung Lin, Jian-Wei Su, Wei‐Chung Lo, Chingwei Yeh, Shyh-Shyuan Sheu, Shih-Hsin Chen and Sih-Han Li and has published in prestigious journals such as IEEE Access, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Shih-Chieh Chang

51 papers receiving 639 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Shih-Chieh Chang Taiwan	15	452	382	182	163	35	55	670
Helia Naeimi United States	16	779 1.7×	415 1.1×	140 0.8×	280 1.7×	44 1.3×	26	908
Kyomin Sohn South Korea	11	305 0.7×	242 0.6×	74 0.4×	195 1.2×	37 1.1×	37	513
André I. Reis Brazil	16	816 1.8×	379 1.0×	81 0.4×	100 0.6×	40 1.1×	109	932
K. Dosaka Japan	11	320 0.7×	293 0.8×	54 0.3×	186 1.1×	19 0.5×	52	500
Renato P. Ribas Brazil	15	736 1.6×	322 0.8×	68 0.4×	94 0.6×	40 1.1×	95	828
Ahmed Sanaullah United States	12	186 0.4×	188 0.5×	110 0.6×	105 0.6×	22 0.6×	28	407
Ivan D. Castellanos United States	4	271 0.6×	199 0.5×	78 0.4×	121 0.7×	16 0.5×	7	385
Michael Bucher United States	6	341 0.8×	185 0.5×	69 0.4×	131 0.8×	46 1.3×	8	446
Priyadarsan Patra United States	11	286 0.6×	194 0.5×	76 0.4×	91 0.6×	16 0.5×	50	443
B. Flachs United States	11	234 0.5×	368 1.0×	38 0.2×	306 1.9×	34 1.0×	17	559

Countries citing papers authored by Shih-Chieh Chang

Since Specialization

Citations

This map shows the geographic impact of Shih-Chieh Chang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shih-Chieh Chang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shih-Chieh Chang more than expected).

Fields of papers citing papers by Shih-Chieh Chang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Shih-Chieh Chang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shih-Chieh Chang. The network helps show where Shih-Chieh Chang may publish in the future.

Co-authorship network of co-authors of Shih-Chieh Chang

This figure shows the co-authorship network connecting the top 25 collaborators of Shih-Chieh Chang. A scholar is included among the top collaborators of Shih-Chieh Chang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Shih-Chieh Chang. Shih-Chieh Chang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Zhang, Jie, Sih-Han Li, Wei‐Chung Lo, et al.. (2024). Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. 1–2. 1 indexed citations

Chang, Tian‐Sheuan, et al.. (2024). CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. 1–5.

Chen, Hui‐Yu, Jui‐Chin Chen, Po‐Chun Yeh, et al.. (2023). GaN on Si RF performance with different AlGaN back barrier. 1–2. 1 indexed citations

Wu, Ping-Chun, Jian-Wei Su, Yen-Lin Chung, et al.. (2023). An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE Journal of Solid-State Circuits. 59(7). 2297–2309. 10 indexed citations

Wu, Ping-Chun, Jian-Wei Su, Jin-Sheng Ren, et al.. (2023). A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE Journal of Solid-State Circuits. 59(1). 196–207. 11 indexed citations

Rahaman, S. Z., Shan-Yi Yang, Yao‐Jen Chang, et al.. (2023). Structure and Performance Co-optimization for the Development of Highly Reliable Spin-Orbit Torque Magnetic Random Access Memory. 8. 1–2. 1 indexed citations

Wu, Ping-Chun, Jian-Wei Su, Yen-Lin Chung, et al.. (2022). A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. 2022 IEEE International Solid- State Circuits Conference (ISSCC). 1–3. 91 indexed citations

Chen, Fang‐Ming, Shan-Yi Yang, Yao‐Jen Chang, et al.. (2020). Fabrication and device characterization of large linear dynamic range tunnel magnetoresistance (TMR) sensors for system applications. 104–105.

Wang, Yunting, et al.. (2019). Aging-aware chip health prediction adopting an innovative monitoring strategy. 179–184. 8 indexed citations

10.

Chen, Yuguang, Michihiro Shintani, Takashi Satō, Yiyu Shi, & Shih-Chieh Chang. (2017). Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. 543–548. 2 indexed citations

11.

Chen, Yuguang, et al.. (2014). Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. Design, Automation, and Test in Europe. 105. 1 indexed citations

12.

Lin, Cheng-Hung, et al.. (2012). Memory-efficient pattern matching architectures using perfect hashing on graphic processing units. 1978–1986. 13 indexed citations

13.

Wu, Kai–Chiang, et al.. (2011). Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. 139–144. 7 indexed citations

14.

Lin, Cheng-Hung, et al.. (2010). Accelerating String Matching Using Multi-Threaded Algorithm on GPU. 1–5. 48 indexed citations

15.

Chang, Shih-Chieh, et al.. (2008). A novel sequential circuit optimization with clock gating logic. International Conference on Computer Aided Design. 2008. 230–233. 10 indexed citations

16.

Chang, Shih-Chieh, et al.. (2008). Timing analysis considering IR drop waveforms in power gating designs. 532–537. 3 indexed citations

17.

Chen, Yu-Ting, et al.. (2007). An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. International Conference on Computer Aided Design. 779–782. 17 indexed citations

18.

Chang, Shih-Chieh, et al.. (2007). An efficient mechanism for performance optimization of variable-latency designs. Proceedings - ACM IEEE Design Automation Conference. 976–976. 20 indexed citations

19.

Todri‐Sanial, Aida, Shih-Chieh Chang, & Malgorzata Marek-Sadowska. (2007). Electromigration and voltage drop aware power grid optimization for power gated ICs. HAL (Le Centre pour la Communication Scientifique Directe). 391–394. 4 indexed citations

20.

Hsieh, Cheng-Tao, et al.. (2005). A vectorless estimation of maximum instantaneous current for sequential circuits. 537–540. 15 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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