Kyu-Myung Choi

916 total citations
62 papers, 637 citations indexed

About

Kyu-Myung Choi is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Kyu-Myung Choi has authored 62 papers receiving a total of 637 indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Electrical and Electronic Engineering, 37 papers in Hardware and Architecture and 16 papers in Computer Networks and Communications. Recurrent topics in Kyu-Myung Choi's work include Low-power high-performance VLSI design (21 papers), Embedded Systems Design Techniques (20 papers) and VLSI and Analog Circuit Testing (19 papers). Kyu-Myung Choi is often cited by papers focused on Low-power high-performance VLSI design (21 papers), Embedded Systems Design Techniques (20 papers) and VLSI and Analog Circuit Testing (19 papers). Kyu-Myung Choi collaborates with scholars based in South Korea, United States and Japan. Kyu-Myung Choi's co-authors include Jeong-Taek Kong, Sungjoo Yoo, Youngsoo Shin, Takayasu Sakurai, Taejoong Song, Kwangok Jeong, Sungpack Hong, Taewhan Kim, Taewhan Kim and Ki‐Tae Park and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Electron Device Letters and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Kyu-Myung Choi

56 papers receiving 598 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Kyu-Myung Choi South Korea	14	485	304	158	34	18	62	637
Shreepad Panth United States	13	597 1.2×	151 0.5×	161 1.0×	21 0.6×	14 0.8×	29	642
Jin-Tai Yan Taiwan	12	511 1.1×	227 0.7×	173 1.1×	42 1.2×	7 0.4×	128	551
Clair Webb United States	9	668 1.4×	355 1.2×	354 2.2×	43 1.3×	9 0.5×	16	807
Eric Karl United States	19	843 1.7×	287 0.9×	130 0.8×	39 1.1×	5 0.3×	41	935
Jeong-Taek Kong South Korea	12	375 0.8×	177 0.6×	77 0.5×	81 2.4×	15 0.8×	62	473
Kai-Yuan Chao United States	15	690 1.4×	377 1.2×	177 1.1×	75 2.2×	20 1.1×	58	760
Umakanta Choudhury India	13	582 1.2×	364 1.2×	41 0.3×	51 1.5×	7 0.4×	32	633
Akram Ben Ahmed Japan	12	446 0.9×	140 0.5×	338 2.1×	20 0.6×	19 1.1×	48	525
Vinay Vashishtha United States	9	591 1.2×	229 0.8×	62 0.4×	40 1.2×	25 1.4×	19	702
Kyung Whan Kim South Korea	6	263 0.5×	122 0.4×	117 0.7×	18 0.5×	23 1.3×	7	328

Countries citing papers authored by Kyu-Myung Choi

Since Specialization

Citations

This map shows the geographic impact of Kyu-Myung Choi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kyu-Myung Choi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kyu-Myung Choi more than expected).

Fields of papers citing papers by Kyu-Myung Choi

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kyu-Myung Choi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kyu-Myung Choi. The network helps show where Kyu-Myung Choi may publish in the future.

Co-authorship network of co-authors of Kyu-Myung Choi

This figure shows the co-authorship network connecting the top 25 collaborators of Kyu-Myung Choi. A scholar is included among the top collaborators of Kyu-Myung Choi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kyu-Myung Choi. Kyu-Myung Choi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Cho, Handong, et al.. (2024). Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. 1–6. 2 indexed citations

Choi, Kyu-Myung, et al.. (2024). DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(8). 2493–2506.

Choi, Kyu-Myung, et al.. (2024). Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. 1–8. 2 indexed citations

Kim, Taehwan, Taehwan Kim, Kwangok Jeong, et al.. (2020). SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integration. 74. 81–92. 1 indexed citations

Kim, Taewhan, et al.. (2018). Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. Asia and South Pacific Design Automation Conference. 500–506. 6 indexed citations

Lim, Chaemoon, Chang-Kyung Ryoo, Kyu-Myung Choi, & Jung‐Hee Cho. (2010). Path generation algorithm for Intelligence, Surveillance and Reconnaissance of an UAV. Society of Instrument and Control Engineers of Japan. 1274–1277. 8 indexed citations

Choi, Kyu-Myung. (2010). An industrial perspective of 3D IC integration technology: from the viewpoint of design technology. Asia and South Pacific Design Automation Conference. 544–545. 4 indexed citations

Choi, Kyu-Myung, et al.. (2009). Design techniques to Minimize the yield loss for general purpose ASIC/SOC Devices. 45–48. 2 indexed citations

Choi, Kyu-Myung, et al.. (2009). 45nm low-power embedded pseudo-SRAM with ECC-based auto-adjusted self-refresh scheme. 2517–2520. 18 indexed citations

10.

Yoo, Sungjoo, et al.. (2008). An industrial perspective of power-aware reliable SoC design. Asia and South Pacific Design Automation Conference. 555–557. 1 indexed citations

11.

Won, Hyosig, et al.. (2007). Thickness Variation Aware Timing Analysis Based on CMP Simulation. 대한전자공학회 ISOCC. 193–195. 1 indexed citations

12.

Choi, Kyu-Myung, et al.. (2007). Gate-Length Biasing for Low Leakage Design. 대한전자공학회 ISOCC. 319–321. 3 indexed citations

13.

Yang, Peng, et al.. (2006). Component-based Transaction-level Power Modeling for ARMACI Crossbar Bus Architecture. 대한전자공학회 ISOCC. 307–310. 3 indexed citations

14.

Hong, Sungpack, et al.. (2005). ViP: A Practical Approach to Platform-based System Modeling Methodology. JSTS Journal of Semiconductor Technology and Science. 5(2). 89–101. 1 indexed citations

15.

Cho, Kwang‐Hyun, et al.. (2005). Multimedia IP Design in SystemC Design Environment Adopting High-level Code Optimization. 대한전자공학회 ISOCC. 24–27. 1 indexed citations

16.

Lee, Jongeun, Woo-Cheol Kwon, Taehun Kim, et al.. (2005). System Level Architecture Evaluation and Optimization: an Industrial Case Study with AMBA3 AXI. JSTS Journal of Semiconductor Technology and Science. 5(4). 229–236. 1 indexed citations

17.

Kim, Young-Taek, et al.. (2005). Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. Design, Automation, and Test in Europe. 138–139. 4 indexed citations

18.

Kim, Youngtaek, et al.. (2004). Fast exploration of parameterized bus architecture for communication-centric SoC design. Design, Automation, and Test in Europe. 1. 10352. 13 indexed citations

19.

Jeong, Kwangok, et al.. (2003). An MTCMOS design methodology and its application to mobile computing. 110–115. 5 indexed citations

20.

Choi, Kyu-Myung & Steven P. Levitan. (1999). A flexible datapath allocation method for architectural synthesis. ACM Transactions on Design Automation of Electronic Systems. 4(4). 376–404. 9 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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