Kun-Han Tsai

1.8k total citations
75 papers, 1.4k citations indexed

About

Kun-Han Tsai is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Kun-Han Tsai has authored 75 papers receiving a total of 1.4k indexed citations (citations by other indexed papers that have themselves been cited), including 72 papers in Electrical and Electronic Engineering, 62 papers in Hardware and Architecture and 12 papers in Control and Systems Engineering. Recurrent topics in Kun-Han Tsai's work include Integrated Circuits and Semiconductor Failure Analysis (64 papers), VLSI and Analog Circuit Testing (61 papers) and 3D IC and TSV technologies (19 papers). Kun-Han Tsai is often cited by papers focused on Integrated Circuits and Semiconductor Failure Analysis (64 papers), VLSI and Analog Circuit Testing (61 papers) and 3D IC and TSV technologies (19 papers). Kun-Han Tsai collaborates with scholars based in United States, Hungary and Taiwan. Kun-Han Tsai's co-authors include J. Rajski, Wu-Tung Cheng, Malgorzata Marek-Sadowska, N. Tamarapalli, Janusz Rajski, Shi‐Yu Huang, Mark Kassab, Zhiyuan Wang, Nilanjan Mukherjee and Andre Hertwig and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Design and Test and Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015.

In The Last Decade

Kun-Han Tsai

74 papers receiving 1.3k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Kun-Han Tsai United States	18	1.3k	1.2k	202	59	46	75	1.4k
Brion Keller United States	15	1.1k 0.8×	1.0k 0.9×	173 0.9×	32 0.5×	14 0.3×	42	1.1k
P. Nigh United States	17	925 0.7×	892 0.7×	87 0.4×	25 0.4×	20 0.4×	31	972
Grzegorz Mrugalski United States	17	1.1k 0.8×	1.1k 0.9×	191 0.9×	20 0.3×	15 0.3×	66	1.2k
A. Krstić United States	19	877 0.7×	869 0.7×	58 0.3×	58 1.0×	19 0.4×	32	945
Chi-Feng Wu Taiwan	12	572 0.4×	541 0.4×	63 0.3×	29 0.5×	34 0.7×	31	658
Lakshmi Reddy United States	11	668 0.5×	621 0.5×	55 0.3×	48 0.8×	6 0.1×	31	725
Kohei Miyase Japan	19	1.1k 0.8×	1.0k 0.8×	104 0.5×	23 0.4×	6 0.1×	75	1.1k
Sreejit Chakravarty United States	13	507 0.4×	485 0.4×	55 0.3×	27 0.5×	9 0.2×	57	538
Stephen Sunter United States	18	825 0.6×	638 0.5×	46 0.2×	16 0.3×	209 4.5×	45	873
Jeff Rearick United States	12	594 0.4×	609 0.5×	95 0.5×	24 0.4×	12 0.3×	38	638

Countries citing papers authored by Kun-Han Tsai

Since Specialization

Citations

This map shows the geographic impact of Kun-Han Tsai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kun-Han Tsai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kun-Han Tsai more than expected).

Fields of papers citing papers by Kun-Han Tsai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kun-Han Tsai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kun-Han Tsai. The network helps show where Kun-Han Tsai may publish in the future.

Co-authorship network of co-authors of Kun-Han Tsai

This figure shows the co-authorship network connecting the top 25 collaborators of Kun-Han Tsai. A scholar is included among the top collaborators of Kun-Han Tsai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kun-Han Tsai. Kun-Han Tsai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

1.

Lee, Shih‐Wei, et al.. (2019). Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(10). 3044–3055. 3 indexed citations

2.

Lee, Shih‐Wei, et al.. (2019). Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. 341–346. 15 indexed citations

3.

Tsai, Kun-Han, et al.. (2018). GPGPU-Based ATPG System: Myth or Reality?. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(1). 239–247. 1 indexed citations

4.

Tsai, Kun-Han, et al.. (2017). Test Coverage Analysis for Designs with Timing Exceptions. 169–174. 4 indexed citations

5.

Tsai, Kun-Han. (2016). Test coverage debugging for designs with timing exception paths. 1–4. 2 indexed citations

6.

Huang, Shi‐Yu, et al.. (2015). Feedback-Bus Oscillation Ring: A General Architecture for Delay Characterization and Test of Interconnects. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. 924–927. 1 indexed citations

7.

Tsai, Kun-Han & Xijiang Lin. (2013). Multicycle-aware At-speed Test Methodology. 49–49. 4 indexed citations

8.

Huang, Shi‐Yu, et al.. (2013). Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. 1–8. 16 indexed citations

9.

Tsai, Kun-Han, et al.. (2012). A unified method for parametric fault characterization of post-bond TSVs. 1–10. 11 indexed citations

10.

Huang, Shi‐Yu, et al.. (2012). Programmable Leakage Test and Binning for TSVs. 43–48. 4 indexed citations

11.

Guo, Ruifeng, et al.. (2010). Scan based speed-path debug for a microprocessor. 207–212. 9 indexed citations

12.

Marek-Sadowska, Malgorzata, et al.. (2009). Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28(2). 245–258. 22 indexed citations

13.

Tsai, Kun-Han, Ruifeng Guo, & Wu-Tung Cheng. (2008). A Robust Automated Scan Pattern Mismatch Debugger. 309–314. 3 indexed citations

14.

McLaurin, Teresa, et al.. (2007). Enhanced testing of clock faults. 1–9. 10 indexed citations

15.

Tsai, Kun-Han, et al.. (2007). Test Generation in the Presence of Timing Exceptions and Constraints. Proceedings - ACM IEEE Design Automation Conference. 688–693. 2 indexed citations

16.

Lin, Xijiang, Kun-Han Tsai, Chen Wang, et al.. (2006). Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. 139–146. 108 indexed citations

17.

Tsai, Kun-Han, et al.. (2006). Built-in constraint resolution. 697–706. 4 indexed citations

18.

Wang, Zhiyuan, Malgorzata Marek-Sadowska, Kun-Han Tsai, & Janusz Rajski. (2006). Analysis and methodology for multiple-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(3). 558–575. 39 indexed citations

19.

Marek-Sadowska, Malgorzata, et al.. (2004). Delay fault diagnosis using timing information. 485–490. 9 indexed citations

20.

Rajski, J., Jerzy Tyszer, Mark Kassab, et al.. (2003). Embedded deterministic test for low cost manufacturing test. 301–310. 321 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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