Xijiang Lin

1.2k total citations
51 papers, 965 citations indexed

About

Xijiang Lin is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, Xijiang Lin has authored 51 papers receiving a total of 965 indexed citations (citations by other indexed papers that have themselves been cited), including 51 papers in Hardware and Architecture, 51 papers in Electrical and Electronic Engineering and 7 papers in Control and Systems Engineering. Recurrent topics in Xijiang Lin's work include VLSI and Analog Circuit Testing (51 papers), Integrated Circuits and Semiconductor Failure Analysis (49 papers) and Radiation Effects in Electronics (11 papers). Xijiang Lin is often cited by papers focused on VLSI and Analog Circuit Testing (51 papers), Integrated Circuits and Semiconductor Failure Analysis (49 papers) and Radiation Effects in Electronics (11 papers). Xijiang Lin collaborates with scholars based in United States, Hungary and Germany. Xijiang Lin's co-authors include Janusz Rajski, S.M. Reddy, Irith Pomeranz, J. Rajski, Mark Kassab, Zhuo Zhang, Rob Thompson, Yu Huang, Jerzy Tyszer and Dariusz Czysz and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Xijiang Lin

49 papers receiving 914 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Xijiang Lin United States	18	944	937	120	34	15	51	965
P. Wohl United States	15	708 0.8×	688 0.7×	112 0.9×	33 1.0×	12 0.8×	38	722
Brion Keller United States	15	1.0k 1.1×	1.1k 1.1×	173 1.4×	32 0.9×	29 1.9×	42	1.1k
Vivek Chickermane United States	15	573 0.6×	597 0.6×	50 0.4×	19 0.6×	14 0.9×	43	623
Kohei Miyase Japan	19	1.0k 1.1×	1.1k 1.1×	104 0.9×	23 0.7×	29 1.9×	75	1.1k
Jeff Rearick United States	12	609 0.6×	594 0.6×	95 0.8×	24 0.7×	27 1.8×	38	638
F. P. M. Beenker Netherlands	10	491 0.5×	480 0.5×	67 0.6×	30 0.9×	42 2.8×	19	520
Seongmoon Wang United States	17	907 1.0×	902 1.0×	135 1.1×	17 0.5×	21 1.4×	38	929
J. Saxena United States	11	898 1.0×	903 1.0×	135 1.1×	19 0.6×	10 0.7×	20	919
I. Hartanto United States	8	373 0.4×	357 0.4×	68 0.6×	38 1.1×	11 0.7×	15	386
E. Volkerink United States	10	390 0.4×	381 0.4×	70 0.6×	18 0.5×	14 0.9×	12	402

Countries citing papers authored by Xijiang Lin

Since Specialization

Citations

This map shows the geographic impact of Xijiang Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xijiang Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xijiang Lin more than expected).

Fields of papers citing papers by Xijiang Lin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xijiang Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xijiang Lin. The network helps show where Xijiang Lin may publish in the future.

Co-authorship network of co-authors of Xijiang Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Xijiang Lin. A scholar is included among the top collaborators of Xijiang Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xijiang Lin. Xijiang Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Pomeranz, Irith & Xijiang Lin. (2020). Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(2). 423–433. 1 indexed citations

Wang, Nai‐Xing, Bo Yao, Xijiang Lin, & Irith Pomeranz. (2017). Functional Broadside Test Generation Using a Commercial ATPG Tool. 14. 308–313. 2 indexed citations

Lin, Xijiang, Mark Kassab, & Janusz Rajski. (2014). Using dynamic shift to reduce test data volume in high-compression designs. 52. 1–6. 5 indexed citations

Xiang, Dong, Jianbo Li, Krishnendu Chakrabarty, & Xijiang Lin. (2013). Test compaction for small-delay defects using an effective path selection scheme. ACM Transactions on Design Automation of Electronic Systems. 18(3). 1–23. 22 indexed citations

Tsai, Kun-Han & Xijiang Lin. (2013). Multicycle-aware At-speed Test Methodology. 49–49. 4 indexed citations

Lin, Xijiang. (2012). Power Supply Droop and Its Impacts on Structural At-Speed Testing. 239–244. 7 indexed citations

Lin, Xijiang, et al.. (2011). Power Aware Embedded Test. 511–516. 5 indexed citations

Lin, Xijiang. (2011). Low power testing - What can commercial DFT tools provide?. 1–6. 1 indexed citations

Lin, Xijiang & J. Rajski. (2010). Adaptive Low Shift Power Test Pattern Generator for Logic BIST. 355–360. 26 indexed citations

10.

Czysz, Dariusz, Mark Kassab, Xijiang Lin, et al.. (2009). Low-Power Scan Operation in Test Compression Environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28(11). 1742–1755. 46 indexed citations

11.

Czysz, Dariusz, Mark Kassab, Xijiang Lin, et al.. (2008). Low Power Scan Shift and Capture in the EDT Environment. 25. 1–10. 46 indexed citations

12.

Huang, Yu, et al.. (2008). Reducing Scan Shift Power at RTL. 20. 139–146. 8 indexed citations

13.

Guo, Ruifeng, et al.. (2008). Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE. Proceedings - International Symposium for Testing and Failure Analysis. 30910. 383–389. 1 indexed citations

14.

Lin, Xijiang, Mark Kassab, & J. Rajski. (2007). Test Generation for Timing-Critical Transition Faults. 493–500. 18 indexed citations

15.

Lin, Xijiang, et al.. (2007). Scan-Based Tests with Low Switching Activity. IEEE Design & Test of Computers. 24(3). 268–275. 19 indexed citations

16.

Lin, Xijiang, Kun-Han Tsai, Chen Wang, et al.. (2006). Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. 139–146. 108 indexed citations

17.

Lin, Xijiang, et al.. (2006). Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. 1–10. 195 indexed citations

18.

Beck, Mattias, et al.. (2005). Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. Design, Automation, and Test in Europe. 56–61. 34 indexed citations

19.

Beck, Mattias, et al.. (2005). Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. 223–228. 9 indexed citations

20.

Wang, Chen, S.M. Reddy, Irith Pomeranz, Xijiang Lin, & J. Rajski. (2002). Conflict driven techniques for improving deterministic test pattern generation. Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design. 87–93. 16 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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