Xijiang Lin

1.2k total citations
51 papers, 965 citations indexed

About

Xijiang Lin is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, Xijiang Lin has authored 51 papers receiving a total of 965 indexed citations (citations by other indexed papers that have themselves been cited), including 51 papers in Hardware and Architecture, 51 papers in Electrical and Electronic Engineering and 7 papers in Control and Systems Engineering. Recurrent topics in Xijiang Lin's work include VLSI and Analog Circuit Testing (51 papers), Integrated Circuits and Semiconductor Failure Analysis (49 papers) and Radiation Effects in Electronics (11 papers). Xijiang Lin is often cited by papers focused on VLSI and Analog Circuit Testing (51 papers), Integrated Circuits and Semiconductor Failure Analysis (49 papers) and Radiation Effects in Electronics (11 papers). Xijiang Lin collaborates with scholars based in United States, Hungary and Germany. Xijiang Lin's co-authors include Janusz Rajski, S.M. Reddy, Irith Pomeranz, J. Rajski, Mark Kassab, Zhuo Zhang, Rob Thompson, Yu Huang, Jerzy Tyszer and Dariusz Czysz and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Xijiang Lin

49 papers receiving 914 citations

Peers

Countries citing papers authored by Xijiang Lin

Since Specialization

Citations

This map shows the geographic impact of Xijiang Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xijiang Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xijiang Lin more than expected).

Fields of papers citing papers by Xijiang Lin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xijiang Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xijiang Lin. The network helps show where Xijiang Lin may publish in the future.

Co-authorship network of co-authors of Xijiang Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Xijiang Lin. A scholar is included among the top collaborators of Xijiang Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xijiang Lin. Xijiang Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Title	Journal	Authors	Indexed citations
1	Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults	IEEE Transactions on Very Large Scale Integration (VLSI) Systems	Irith Pomeranz, Xijiang Lin	1
2	Functional Broadside Test Generation Using a Commercial ATPG Tool		Nai‐Xing Wang, Bo Yao et al.	2
3	Using dynamic shift to reduce test data volume in high-compression designs		Xijiang Lin, Mark Kassab et al.	5
4	Test compaction for small-delay defects using an effective path selection scheme	ACM Transactions on Design Automation of Electronic Systems	Dong Xiang, Jianbo Li et al.	22
5	Multicycle-aware At-speed Test Methodology		Kun-Han Tsai, Xijiang Lin	4
6	Power Supply Droop and Its Impacts on Structural At-Speed Testing		Xijiang Lin	7
7	Power Aware Embedded Test		Xijiang Lin, Nilanjan Mukherjee et al.	5
8	Low power testing - What can commercial DFT tools provide?		Xijiang Lin	1
9	Adaptive Low Shift Power Test Pattern Generator for Logic BIST		Xijiang Lin, J. Rajski	26
10	Low-Power Scan Operation in Test Compression Environment	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	Dariusz Czysz, Mark Kassab et al.	46
11	Low Power Scan Shift and Capture in the EDT Environment		Dariusz Czysz, Mark Kassab et al.	46
12	Reducing Scan Shift Power at RTL		Yu Huang, Xijiang Lin et al.	8
13	Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE	Proceedings - International Symposium for Testing and Failure Analysis	Ruifeng Guo, Wu-Tung Cheng et al.	1
14	Test Generation for Timing-Critical Transition Faults		Xijiang Lin, Mark Kassab et al.	18
15	Scan-Based Tests with Low Switching Activity	IEEE Design & Test of Computers	Xijiang Lin, S.M. Reddy et al.	19
16	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects		Xijiang Lin, Kun-Han Tsai et al.	108
17	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs		Xijiang Lin, Zhuo Zhang et al.	195
18	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality	Design, Automation, and Test in Europe	Mattias Beck, Xijiang Lin et al.	34
19	Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study		Mattias Beck, Xijiang Lin et al.	9
20	Conflict driven techniques for improving deterministic test pattern generation	Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design	Chen Wang, S.M. Reddy et al.	16

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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