Xijiang Lin

1.2k citations

51 papers · 965 indexed · h-index 18

Hardware and Architecture top 0.5%
Electrical and Electronic Engineering top 5%
Control and Systems Engineering top 10%
Software top 10%
Computer Networks and Communications

Co-authors: Janusz Rajski S.M. Reddy Irith Pomeranz J. Rajski Mark Kassab Zhuo Zhang Rob Thompson Yu Huang
Topics: VLSI and Analog Circuit Testing (51 papers)Integrated Circuits and Semiconductor Failure Analysis (49 papers)Radiation Effects in Electronics (11 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Software
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Very Large Scale Integration (VLSI) Systems ACM Transactions on Design Automation of Electronic Systems
Partner nations: United States Hungary Germany

In The Last Decade

Xijiang Lin

49 papers receiving 914 citations

Peers

Countries citing papers authored by Xijiang Lin

Since Specialization

Citations

This map shows the geographic impact of Xijiang Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xijiang Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xijiang Lin more than expected).

Fields of papers citing papers by Xijiang Lin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xijiang Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xijiang Lin. The network helps show where Xijiang Lin may publish in the future.

Co-authorship network of co-authors of Xijiang Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Xijiang Lin. A scholar is included among the top collaborators of Xijiang Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xijiang Lin. Xijiang Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults 2020 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Irith Pomeranz,Xijiang Lin	1
2	Functional Broadside Test Generation Using a Commercial ATPG Tool 2017 ·Nai‐Xing Wang,Bo Yao,Xijiang Lin,Irith Pomeranz	2
3	Using dynamic shift to reduce test data volume in high-compression designs 2014 ·Xijiang Lin,Mark Kassab,Janusz Rajski	5
4	Test compaction for small-delay defects using an effective path selection scheme 2013 ·ACM Transactions on Design Automation of Electronic Systems ·Dong Xiang,Jianbo Li,Krishnendu Chakrabarty,Xijiang Lin	22
5	Multicycle-aware At-speed Test Methodology 2013 ·Kun-Han Tsai,Xijiang Lin	4
6	Power Supply Droop and Its Impacts on Structural At-Speed Testing 2012 ·Xijiang Lin	7
7	Power Aware Embedded Test 2011 ·Xijiang Lin,(unknown),Nilanjan Mukherjee,Benoit Nadeau-Dostie,Janusz Rajski,Jerzy Tyszer	5
8	Low power testing - What can commercial DFT tools provide? 2011 ·Xijiang Lin	1
9	Adaptive Low Shift Power Test Pattern Generator for Logic BIST 2010 ·Xijiang Lin,J. Rajski	26
10	Low-Power Scan Operation in Test Compression Environment 2009 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Dariusz Czysz,Mark Kassab,Xijiang Lin,Grzegorz Mrugalski,Janusz Rajski,Jerzy Tyszer	46
11	Low Power Scan Shift and Capture in the EDT Environment 2008 ·Dariusz Czysz,Mark Kassab,Xijiang Lin,Grzegorz Mrugalski,Janusz Rajski,Jerzy Tyszer	46
12	Reducing Scan Shift Power at RTL 2008 ·(unknown),Yu Huang,Xijiang Lin,Wu-Tung Cheng,Jennifer Dworak	8
13	Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE 2008 ·Proceedings - International Symposium for Testing and Failure Analysis ·(unknown),Ruifeng Guo,Wu-Tung Cheng,Xijiang Lin,Brady Benware	1
14	Test Generation for Timing-Critical Transition Faults 2007 ·Xijiang Lin,Mark Kassab,J. Rajski	18
15	Scan-Based Tests with Low Switching Activity 2007 ·IEEE Design & Test of Computers ·(unknown),Xijiang Lin,S.M. Reddy,Irith Pomeranz,Janusz Rajski	19
16	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects 2006 ·Xijiang Lin,Kun-Han Tsai,Chen Wang,Mark Kassab,J. Rajski,Takeo Kobayashi,(unknown),Yasuo Satô,Shuji Hamada,(unknown)	108
17	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs 2006 ·(unknown),Xijiang Lin,Zhuo Zhang,S.M. Reddy,Irith Pomeranz,Janusz Rajski	195
18	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality 2005 ·Design, Automation, and Test in Europe ·Mattias Beck,(unknown),(unknown),(unknown),Xijiang Lin,(unknown)	34
19	Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study 2005 ·Mattias Beck,(unknown),(unknown),Xijiang Lin,(unknown)	9
20	Conflict driven techniques for improving deterministic test pattern generation 2002 ·Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design ·Chen Wang,S.M. Reddy,Irith Pomeranz,Xijiang Lin,J. Rajski	16

About Xijiang Lin

Xijiang Lin is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering, having authored 51 papers that have together received 965 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (51 papers), Integrated Circuits and Semiconductor Failure Analysis (49 papers) and Radiation Effects in Electronics (11 papers). The work is most often cited by research in Hardware and Architecture (944 citations), Electrical and Electronic Engineering (937 citations) and Software (34 citations). Xijiang Lin has collaborated with scholars based in United States, Hungary and Germany. Frequent co-authors include Janusz Rajski, S.M. Reddy, Irith Pomeranz, J. Rajski, Mark Kassab, Zhuo Zhang, Rob Thompson, Yu Huang, Jerzy Tyszer and Dariusz Czysz. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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