Kohei Miyase

1.4k citations

75 papers · 1.1k indexed · h-index 19

Electrical and Electronic Engineering top 5%
Hardware and Architecture top 0.5%
Control and Systems Engineering top 10%
Computer Networks and Communications
Software top 10%

Co-authors: Seiji Kajihara Xiaoqing Wen S.M. Reddy Kewal K. Saluja Irith Pomeranz Laung‐Terng Wang Kunio Ishida Tatsuya Suzuki
Topics: VLSI and Analog Circuit Testing (63 papers)Integrated Circuits and Semiconductor Failure Analysis (62 papers)Advancements in Photolithography Techniques (16 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Software
Journals: IEEE Transactions on Aerospace and Electronic Systems IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ACM Transactions on Design Automation of Electronic Systems
Partner nations: Japan United States Germany

In The Last Decade

Kohei Miyase

73 papers receiving 1.1k citations

Peers

Countries citing papers authored by Kohei Miyase

Since Specialization

Citations

This map shows the geographic impact of Kohei Miyase's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kohei Miyase with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kohei Miyase more than expected).

Fields of papers citing papers by Kohei Miyase

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kohei Miyase. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kohei Miyase. The network helps show where Kohei Miyase may publish in the future.

Co-authorship network of co-authors of Kohei Miyase

This figure shows the co-authorship network connecting the top 25 collaborators of Kohei Miyase. A scholar is included among the top collaborators of Kohei Miyase based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kohei Miyase. Kohei Miyase is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments 2019 ·IEEE Transactions on Aerospace and Electronic Systems ·Aibin Yan,(unknown),(unknown),(unknown),Jie Cui,Zhili Chen,Kohei Miyase,Xiaoqing Wen	75
2	A Static Method for Analyzing Hotspot Distribution on the LSI 2019 ·Kohei Miyase,(unknown),Shyue-Kung Lu,Xiaoqing Wen,Seiji Kajihara	0
3	Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM 2019 ·Journal of Electronic Testing ·Shyue-Kung Lu,(unknown),Chun‐Lung Hsu,(unknown),Kohei Miyase	2
4	Analysis and mitigation or IR-Drop induced scan shift-errors 2017 ·Stefan Holst,Eric Schneider,(unknown),Michael A. Kochte,Kohei Miyase,Hans-Joachim Wunderlich,Seiji Kajihara,Xiaoqing Wen	7
5	Identification of high power consuming areas with gate type and logic level information 2015 ·Kohei Miyase,Matthias Sauer,Bernd Becker,Xiaoqing Wen,Seiji Kajihara	12
6	Soft-error tolerant TCAMs for high-reliability packet classifications 2014 ·Infall Syafalni,Tsutomu Sasao,Xiaoqing Wen,Stefan Holst,Kohei Miyase	9
7	Low Power BIST for Scan-Shift and Capture Power 2012 ·Yasuo Satô,(unknown),(unknown),Kohei Miyase,Seiji Kajihara	25
8	LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing 2012 ·IEEE Design and Test ·(unknown),Kohei Miyase,Seiji Kajihara,Xiaoqing Wen,Laung‐Terng Wang,Michael A. Kochte	6
9	SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures 2011 ·Michael A. Kochte,Kohei Miyase,Xiaoqing Wen,Seiji Kajihara,(unknown),(unknown),Hans-Joachim Wunderlich	3
10	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing 2011 ·IEICE Transactions on Information and Systems ·Kohei Miyase,K. Noda,(unknown),Kazumi Hatayama,(unknown),(unknown),Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara	1
11	Transition-Time-Relation based capture-safety checking for at-speed scan test generation 2011 ·Kohei Miyase,Xiaoqing Wen,(unknown),Hidemitsu Furukawa,(unknown),Seiji Kajihara	3
12	Is test power reduction through X-filling good enough? 2010 ·(unknown),Luigi Dilillo,Alberto Bosio,Patrick Girard,S. Pravossoudovitch,A. Virazel,Mark Tehranipoor,Kohei Miyase,Xiaoqing Wen,Nisar Ahmed	5
13	Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment 2009 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Jiun-Lang Huang,Xiaoqing Wen,Kohei Miyase	11
14	A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing 2009 ·(unknown),Xiaoqing Wen,Kohei Miyase,Hiroshi Furukawa,Seiji Kajihara	7
15	Diagnosis of Realistic Defects Based on the X-Fault Model 2008 ·Ilia Polian,Yusuke Nakamura,(unknown),(unknown),Kohei Miyase,Seiji Kajihara,Bernd Becker,Xiaoqing Wen	5
16	A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation 2006 ·Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,(unknown),Seiji Kajihara,Laung‐Terng Wang,Kewal K. Saluja	38
17	Don't Care Identification and Statistical Encoding for Test Data Compression 2004 ·IEICE Transactions on Information and Systems ·Seiji Kajihara,(unknown),Kohei Miyase,Irith Pomeranz,S.M. Reddy	1
18	On test data volume reduction for multiple scan chain designs 2003 ·ACM Transactions on Design Automation of Electronic Systems ·S.M. Reddy,Kohei Miyase,Seiji Kajihara,Irith Pomeranz	7
19	Average Power Reduction in Scan Testing by Test Vector Modification 2002 ·IEICE Transactions on Information and Systems ·Seiji Kajihara,Kōji Ishida,Kohei Miyase	1
20	On identifying don't care inputs of test patterns for combinational circuits 2001 ·International Conference on Computer Aided Design ·Seiji Kajihara,Kohei Miyase	55

About Kohei Miyase

Kohei Miyase is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Software, having authored 75 papers that have together received 1.1k indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (63 papers), Integrated Circuits and Semiconductor Failure Analysis (62 papers) and Advancements in Photolithography Techniques (16 papers). The work is most often cited by research in Hardware and Architecture (1.0k citations), Electrical and Electronic Engineering (1.1k citations) and Software (23 citations). Kohei Miyase has collaborated with scholars based in Japan, United States and Germany. Frequent co-authors include Seiji Kajihara, Xiaoqing Wen, S.M. Reddy, Kewal K. Saluja, Irith Pomeranz, Laung‐Terng Wang, Kunio Ishida, Tatsuya Suzuki, Patrick Girard and Yasuo Satô. Their work appears in journals such as IEEE Transactions on Aerospace and Electronic Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and ACM Transactions on Design Automation of Electronic Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact