Mark Kassab

2.1k citations

49 papers · 1.6k indexed · 1 hit paper · h-index 16

Impact in

Hardware and Architecture top 0.2%
- VLSI and Analog Circuit Testing
- Physical Unclonable Functions (PUFs) and Hardware Security
Electrical and Electronic Engineering top 2%
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and FPGA Design Techniques
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Advancements in Photolithography Techniques

Papers in ⓘ

Electrical and Electronic Engineering 49
- Integrated Circuits and Semiconductor Failure Analysis 46
- VLSI and FPGA Design Techniques 16
- Low-power high-performance VLSI design 6
- Radiation Effects in Electronics 5
- Advancements in Photolithography Techniques 5
Hardware and Architecture 48
- VLSI and Analog Circuit Testing 48

Co-authors: Jerzy Tyszer (21 shared papers)Janusz Rajski (30 shared papers)Nilanjan Mukherjee (19 shared papers)J. Rajski (11 shared papers)N. Tamarapalli (4 shared papers)Grzegorz Mrugalski (11 shared papers)Kun-Han Tsai (7 shared papers)Xijiang Lin (9 shared papers)
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (7 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)Proceedings - ACM IEEE Design Automation Conference (2 papers)Design, Automation, and Test in Europe (1 paper)IEEE Design & Test of Computers (2 papers)
Partner nations: United States Hungary Poland

In The Last Decade

Mark Kassab

45 papers receiving 1.5k citations

Hit Papers

align trajectories log scale

Embedded Deterministic Test 2004 · 387 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Peers

Countries citing papers authored by Mark Kassab

Since Specialization

Citations

This map shows the geographic impact of Mark Kassab's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mark Kassab with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mark Kassab more than expected).

Fields of papers citing papers by Mark Kassab

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mark Kassab. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mark Kassab. The network helps show where Mark Kassab may publish in the future.

Co-authors

The 25 scholars most cited alongside Mark Kassab, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Mark Kassab Line = papers co-authored together Mark Kassab links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 49 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Embedded Deterministic Test IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee Hit paper breakdown →	2004	387
2	Embedded deterministic test for low cost manufacturing test J. Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Robert G. Thompson, Kun-Han Tsai, Andre Hertwig, N. Tamarapalli, Grzegorz Mrugalski, Geir Egil Eide, Jun Qian	2003	321
3	Logic BIST for large industrial designs: real issues and case studies G. Hetherington, T. Fryars, N. Tamarapalli, Mark Kassab, A.S.M. Hassan, J. Rajski	2003	198
4	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, J. Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Satô, Shuji Hamada, Takashi Aikyo	2006	108
5	At-speed scan test with low switching activity Elham Moghaddam, Janusz Rajski, Mark Kassab, S.M. Reddy	2010	60
6	Embedded deterministic test for low-cost manufacturing IEEE Design & Test of Computers ·Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, N. Tamarapalli, Jerzy Tyszer, Jun Qian	2003	51
7	Low-Power Scan Operation in Test Compression Environment IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	2009	46
8	Low Power Scan Shift and Capture in the EDT Environment Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	2008	46
9	X-Press Compactor for 1000x Reduction of Test Data Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab	2006	42
10	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab	2007	38
11	Affordable and effective screening of delay defects in ASICs using the inline resistance fault model Brady Benware, Cheng-Tse Lu, John Van Slyke, P. Krishnamurthy, R. Madge, Martin Keim, Mark Kassab, Janusz Rajski	2005	26
12	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Egil Eide, Janusz Rajski, Glenn Colon-Bonet, Naveen Mysore, Yin Ya, P. Pant	2020	22
13	A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab	2011	20
14	Test Generation for Timing-Critical Transition Faults Xijiang Lin, Mark Kassab, J. Rajski	2007	18
15	Isometric Test Data Compression IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Amit Kumar, Mark Kassab, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, S.M. Reddy, Jerzy Tyszer, Chen Wang	2015	16
16	Industrial experience with adoption of edt for low-cost test without concessions F. Poehl, Michel van Beek, N. Tamarapalli, Mark Kassab, R. Arnold, P. Muhmenthaler, Nilanjan Mukherjee, J. Rajski	2004	15
17	EDT Bandwidth Management in SoC Designs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	2012	15
18	Dynamic channel allocation for higher EDT compression in SoC designs Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer	2010	14
19	EDT bandwidth management - Practical scenarios for large SoC designs Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yanhao Dong, Grady Giles	2013	14
20	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism Jakub Janicki, Jerzy Tyszer, A. Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski	2011	13

About Mark Kassab

Mark Kassab is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Control and Systems Engineering, Mechanical Engineering and Software, having authored 49 papers that have together received 1.6k indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (48 papers), Integrated Circuits and Semiconductor Failure Analysis (46 papers), VLSI and FPGA Design Techniques (16 papers), Engineering and Test Systems (11 papers), Low-power high-performance VLSI design (6 papers), Radiation Effects in Electronics (5 papers), Advancements in Photolithography Techniques (5 papers) and Non-Destructive Testing Techniques (2 papers). The work is most often cited by research in Hardware and Architecture (1.6k citations), Electrical and Electronic Engineering (1.5k citations), Software (49 citations), Control and Systems Engineering (242 citations) and Computer Networks and Communications (43 citations). Mark Kassab has collaborated with scholars based in United States, Hungary and Poland. Frequent co-authors include Jerzy Tyszer, Janusz Rajski, Nilanjan Mukherjee, J. Rajski, N. Tamarapalli, Grzegorz Mrugalski, Kun-Han Tsai, Xijiang Lin, Jun Qian and A.S.M. Hassan. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Proceedings - ACM IEEE Design Automation Conference, Design, Automation, and Test in Europe and IEEE Design & Test of Computers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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