Vivek Chickermane

947 total citations
43 papers, 623 citations indexed

About

Vivek Chickermane is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Vivek Chickermane has authored 43 papers receiving a total of 623 indexed citations (citations by other indexed papers that have themselves been cited), including 43 papers in Electrical and Electronic Engineering, 42 papers in Hardware and Architecture and 5 papers in Control and Systems Engineering. Recurrent topics in Vivek Chickermane's work include VLSI and Analog Circuit Testing (42 papers), Integrated Circuits and Semiconductor Failure Analysis (40 papers) and Radiation Effects in Electronics (8 papers). Vivek Chickermane is often cited by papers focused on VLSI and Analog Circuit Testing (42 papers), Integrated Circuits and Semiconductor Failure Analysis (40 papers) and Radiation Effects in Electronics (8 papers). Vivek Chickermane collaborates with scholars based in United States, Belgium and Netherlands. Vivek Chickermane's co-authors include J.H. Patel, Brion Keller, B. E. Foutz, E.M. Rudnick, Erik Jan Marinissen, Prithviraj Banerjee, Patrick Gallagher, Sandeep Goel, Sergej Deutsch and Ashok Mehta and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Design and Test.

In The Last Decade

Vivek Chickermane

41 papers receiving 593 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Vivek Chickermane United States 15 597 573 50 19 14 43 623
G. Gronthoud Netherlands 12 447 0.7× 429 0.7× 35 0.7× 11 0.6× 11 0.8× 26 470
Sreejit Chakravarty United States 13 507 0.8× 485 0.8× 55 1.1× 27 1.4× 19 1.4× 57 538
E. Volkerink United States 10 381 0.6× 390 0.7× 70 1.4× 18 0.9× 14 1.0× 12 402
G. Hetherington United States 6 447 0.7× 451 0.8× 65 1.3× 8 0.4× 20 1.4× 8 466
Rubin Parekhji India 12 312 0.5× 293 0.5× 33 0.7× 19 1.0× 29 2.1× 65 332
B. Kruseman Netherlands 14 576 1.0× 516 0.9× 31 0.6× 12 0.6× 6 0.4× 35 600
Jeff Rearick United States 12 594 1.0× 609 1.1× 95 1.9× 24 1.3× 27 1.9× 38 638
Anuja Sehgal United States 12 282 0.5× 285 0.5× 28 0.6× 10 0.5× 30 2.1× 22 306
I. Hartanto United States 8 357 0.6× 373 0.7× 68 1.4× 38 2.0× 11 0.8× 15 386
Urban Ingelsson Sweden 10 276 0.5× 285 0.5× 43 0.9× 8 0.4× 27 1.9× 25 307

Countries citing papers authored by Vivek Chickermane

Since Specialization
Citations

This map shows the geographic impact of Vivek Chickermane's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Vivek Chickermane with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Vivek Chickermane more than expected).

Fields of papers citing papers by Vivek Chickermane

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Vivek Chickermane. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Vivek Chickermane. The network helps show where Vivek Chickermane may publish in the future.

Co-authorship network of co-authors of Vivek Chickermane

This figure shows the co-authorship network connecting the top 25 collaborators of Vivek Chickermane. A scholar is included among the top collaborators of Vivek Chickermane based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Vivek Chickermane. Vivek Chickermane is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Rajski, Janusz, et al.. (2023). The Future of Design for Test and Silicon Lifecycle Management. IEEE Design and Test. 41(4). 35–49. 10 indexed citations
2.
Keller, Brion, et al.. (2015). A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Design and Test. 32(4). 40–48. 10 indexed citations
3.
Chickermane, Vivek, et al.. (2015). At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. 79–84. 18 indexed citations
4.
Malik, Anil K., et al.. (2015). A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. 43–48. 2 indexed citations
5.
Keller, Brion, B. E. Foutz, Vivek Chickermane, et al.. (2014). Efficient testing of hierarchical core-based SOCs. 1–10. 11 indexed citations
6.
7.
Deutsch, Sergej, Brion Keller, Vivek Chickermane, et al.. (2012). DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. 1–10. 30 indexed citations
8.
9.
Chickermane, Vivek, et al.. (2008). A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. 1–10. 10 indexed citations
10.
Arima, Shinichi, et al.. (2006). Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. 415–420. 2 indexed citations
11.
Keller, Brion, et al.. (2005). An economic analysis and ROI model for nanometer test. 518–524. 20 indexed citations
12.
Chickermane, Vivek, et al.. (2005). Design for Testability Using Architectural Descriptions. 752–752.
13.
Chickermane, Vivek, et al.. (2005). Practical Aspects of Delay Testing for Nanometer Chips. 470–470. 1 indexed citations
14.
Chickermane, Vivek & J.H. Patel. (2002). A fault oriented partial scan design approach. 400–403. 63 indexed citations
15.
Chickermane, Vivek, et al.. (2002). Impact of high level functional constraints on testability. 309–312. 1 indexed citations
16.
Chickermane, Vivek & J.H. Patel. (2002). An optimization based approach to the partial scan design problem. 377–386. 69 indexed citations
17.
Chickermane, Vivek, et al.. (2002). A building block BIST methodology for SOC designs: a case study. 111–120. 17 indexed citations
18.
Rudnick, E.M., Vivek Chickermane, & J.H. Patel. (1994). An observability enhancement approach for improved testability and at-speed test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13(8). 1051–1056. 26 indexed citations
19.
Chickermane, Vivek, et al.. (1992). A comparative study of design for testability methods using high-level and gate-level descriptions. International Conference on Computer Aided Design. 620–624. 3 indexed citations
20.
Banerjee, P., et al.. (1992). APT: an area-performance-testability driven placement algorithm. Design Automation Conference. 141–146. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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