Jeff Rearick

895 total citations
38 papers, 638 citations indexed

About

Jeff Rearick is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Jeff Rearick has authored 38 papers receiving a total of 638 indexed citations (citations by other indexed papers that have themselves been cited), including 33 papers in Electrical and Electronic Engineering, 31 papers in Hardware and Architecture and 12 papers in Control and Systems Engineering. Recurrent topics in Jeff Rearick's work include Integrated Circuits and Semiconductor Failure Analysis (30 papers), VLSI and Analog Circuit Testing (30 papers) and Engineering and Test Systems (11 papers). Jeff Rearick is often cited by papers focused on Integrated Circuits and Semiconductor Failure Analysis (30 papers), VLSI and Analog Circuit Testing (30 papers) and Engineering and Test Systems (11 papers). Jeff Rearick collaborates with scholars based in United States, Canada and Germany. Jeff Rearick's co-authors include J.H. Patel, P.C. Maxwell, Bill Eklow, Alfred L. Crouch, Anuja Sehgal, Janusz Rajski, Friedrich Hapke, Li-C. Wang, Andreas Glowatz and Jing Zeng and has published in prestigious journals such as IEEE Design and Test and IEEE Design & Test of Computers.

In The Last Decade

Jeff Rearick

35 papers receiving 593 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Jeff Rearick United States 12 609 594 95 27 24 38 638
Sreejit Chakravarty United States 13 485 0.8× 507 0.9× 55 0.6× 19 0.7× 27 1.1× 57 538
Kee Sup Kim United States 11 572 0.9× 770 1.3× 41 0.4× 56 2.1× 19 0.8× 25 799
Kohei Miyase Japan 19 1.0k 1.7× 1.1k 1.8× 104 1.1× 29 1.1× 23 1.0× 75 1.1k
Seongmoon Wang United States 17 907 1.5× 902 1.5× 135 1.4× 21 0.8× 17 0.7× 38 929
Brion Keller United States 15 1.0k 1.7× 1.1k 1.8× 173 1.8× 29 1.1× 32 1.3× 42 1.1k
Vivek Chickermane United States 15 573 0.9× 597 1.0× 50 0.5× 14 0.5× 19 0.8× 43 623
P. Wohl United States 15 708 1.2× 688 1.2× 112 1.2× 12 0.4× 33 1.4× 38 722
J. Saxena United States 11 898 1.5× 903 1.5× 135 1.4× 10 0.4× 19 0.8× 20 919
Kuo-Liang Cheng Taiwan 11 337 0.6× 339 0.6× 57 0.6× 67 2.5× 21 0.9× 23 388
A. Krstić United States 19 869 1.4× 877 1.5× 58 0.6× 31 1.1× 58 2.4× 32 945

Countries citing papers authored by Jeff Rearick

Since Specialization
Citations

This map shows the geographic impact of Jeff Rearick's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jeff Rearick with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jeff Rearick more than expected).

Fields of papers citing papers by Jeff Rearick

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jeff Rearick. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jeff Rearick. The network helps show where Jeff Rearick may publish in the future.

Co-authorship network of co-authors of Jeff Rearick

This figure shows the co-authorship network connecting the top 25 collaborators of Jeff Rearick. A scholar is included among the top collaborators of Jeff Rearick based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jeff Rearick. Jeff Rearick is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Crouch, Alfred L., et al.. (2019). P1687.1: Accessing Embedded 1687 Instruments using Alternate Device Interfaces other than JTAG. 1–7. 3 indexed citations
2.
Dobbelaere, Wim, et al.. (2018). Innovative practices on quality levels of A/MS devices. 1–1. 1 indexed citations
3.
Rearick, Jeff, et al.. (2017). Use models for extending IEEE 1687 to analog test. 1–8. 2 indexed citations
4.
Dong, Yanhao, et al.. (2017). Maximizing scan pin and bandwidth utilization with a scan routing fabric. 1–10. 9 indexed citations
5.
Alfano, Michael P., et al.. (2016). Unleashing Fury: A New Paradigm for 3-D Design and Test. IEEE Design and Test. 34(1). 8–15. 13 indexed citations
6.
Sunter, Stephen, et al.. (2016). Streaming Access to ADCs and DACs for Mixed-Signal ATPG. IEEE Design and Test. 33(6). 38–45. 3 indexed citations
7.
Sunter, Stephen, et al.. (2015). Streaming fast access to ADCs and DACs for mixed-signal ATPG. 1–8. 4 indexed citations
8.
Zeng, Jing, et al.. (2010). Predicting multi-core system Fmax by data-learning methodology. 220–223. 4 indexed citations
9.
Zeng, Jing, et al.. (2010). Selecting the most relevant structural Fmax for system Fmax correlation. 99–104. 20 indexed citations
10.
Sinanoglu, Ozgur, et al.. (2009). Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Design & Test of Computers. 26(3). 25–37. 16 indexed citations
11.
Sehgal, Anuja, et al.. (2007). Test cost reduction for the AMD™ Athlon processor using test partitioning. 13. 1–10. 11 indexed citations
12.
Rearick, Jeff, et al.. (2006). Calibrating clock stretch during AC scan testing. 266–273. 53 indexed citations
13.
Rearick, Jeff, et al.. (2006). IJTAG (Internal JTAG): A Step Toward a DFT Standard. 808–815. 40 indexed citations
14.
Rearick, Jeff. (2003). Practical scan test generation and application for embedded FIFOs. 294–300. 5 indexed citations
15.
Rearick, Jeff. (2002). Buying time for the stuck-at fault model. 1167–1167.
16.
Rearick, Jeff. (2002). The case for partial scan. 1032–1032. 6 indexed citations
17.
Rearick, Jeff & J.H. Patel. (2002). Fast and accurate CMOS bridging fault simulation. 54–62. 53 indexed citations
18.
Kim, Young, et al.. (2002). Frequency detection-based boundary-scan testing of AC coupled nets. 46–53. 6 indexed citations
19.
Rearick, Jeff. (2002). Too much delay fault coverage is a bad thing. 624–633. 201 indexed citations
20.
Maxwell, P.C. & Jeff Rearick. (2002). A simulation-based method for estimating defect-free I/sub DDQ/. 80–84. 12 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Breakdown of academic impact, for papers by Sreejit Chakravarty Breakdown of academic impact, for papers by Kee Sup Kim Breakdown of academic impact, for papers by Kohei Miyase Breakdown of academic impact, for papers by Seongmoon Wang Breakdown of academic impact, for papers by Brion Keller Breakdown of academic impact, for papers by Vivek Chickermane Breakdown of academic impact, for papers by P. Wohl Breakdown of academic impact, for papers by J. Saxena Breakdown of academic impact, for papers by Kuo-Liang Cheng Breakdown of academic impact, for papers by A. Krstić
Rankless by CCL
2026