Sriram Vangal

3.0k citations

29 papers · 2.0k indexed · 3 hit papers · h-index 15

Electrical and Electronic Engineering top 5%
Computer Networks and Communications top 1%
Hardware and Architecture top 0.5%
Electronic, Optical and Magnetic Materials top 10%
Biomedical Engineering

Co-authors: Nitin Borkar Yatin Hoskote Shekhar Borkar James Tschanz Vasantha Erraguntla Saurabh Dighe Jason Howard D. Finan
Topics: Low-power high-performance VLSI design (19 papers)Interconnection Networks and Systems (12 papers)Advancements in Semiconductor Devices and Circuit Design (8 papers)
Cited by: Hardware and Architecture Computer Networks and Communications Electrical and Electronic Engineering
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Micro
Partner nations: United States Sweden India

In The Last Decade

Sriram Vangal

29 papers receiving 1.9k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

2008 466 citations Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 416 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 415 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →

Peers

Countries citing papers authored by Sriram Vangal

Since Specialization

Citations

This map shows the geographic impact of Sriram Vangal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sriram Vangal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sriram Vangal more than expected).

Fields of papers citing papers by Sriram Vangal

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sriram Vangal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sriram Vangal. The network helps show where Sriram Vangal may publish in the future.

Co-authorship network of co-authors of Sriram Vangal

This figure shows the co-authorship network connecting the top 25 collaborators of Sriram Vangal. A scholar is included among the top collaborators of Sriram Vangal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sriram Vangal. Sriram Vangal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities 2021 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Sriram Vangal,Somnath Paul,Steven Hsu,Amit Agarwal,Saurabh Kumar,Ram Krishnamurthy,Harish K. Krishnamurthy,James Tschanz,Vivek De,Chris H. Kim	8
2	Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips 2020 ·Journal of Low Power Electronics and Applications ·Sriram Vangal,Somnath Paul,Steven Hsu,Amit Agarwal,Ram Krishnamurthy,James Tschanz,Vivek De	5
3	A Sub-cm³ Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications 2017 ·IEEE Journal of Solid-State Circuits ·Somnath Paul,(unknown),Ryan Kim,(unknown),Paolo Aseron,(unknown),Robert Sankman,Debendra Mallik,Tao Wang,Sriram Vangal,James Tschanz,Vivek De	46
4	Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era 2016 ·IEEE Design and Test ·Vivek De,Sriram Vangal,Ram Krishnamurthy	26
5	Test implications and challenges in near threshold computing special session 2016 ·Mehdi B. Tahoori,Rob Aitken,Sriram Vangal,(unknown)	1
6	An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS 2016 ·Somnath Paul,(unknown),Ryan Kim,(unknown),Paolo Aseron,(unknown),Robert Sankman,Debendra Mallik,Sandeep Jain,Sriram Vangal,James Tschanz,Vivek De	19
7	Resiliency for many-core system on a chip 2014 ·Tanay Karnik,James Tschanz,Nitin Borkar,Jason Howard,Sriram Vangal,Vivek De,Shekhar Borkar	2
8	IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS 2013 ·IEEE Micro ·(unknown),Saurabh Dighe,Shailendra Jain,(unknown),Sriram Vangal	11
9	A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping 2011 ·Saurabh Dighe,Sumeet Kumar Gupta,Vivek De,Sriram Vangal,Nitin Borkar,Shekhar Borkar,Kaushik Roy	12
10	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor 2010 ·IEEE Journal of Solid-State Circuits ·Saurabh Dighe,Sriram Vangal,Paolo Aseron,Sachin Sharma Ashok Kumar,Tiju Jacob,Keith Bowman,Jason Howard,James Tschanz,Vasantha Erraguntla,Nitin Borkar,Vivek De,Shekhar Borkar	95
11	An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOSbreakdown → 2008 ·IEEE Journal of Solid-State Circuits ·Sriram Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James Tschanz,D. Finan,(unknown),Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar	466
12	A 5-GHz Mesh Interconnect for a Teraflops Processorbreakdown → 2007 ·IEEE Micro ·Yatin Hoskote,Sriram Vangal,(unknown),Nitin Borkar,Shekhar Borkar	415
13	A 5.1GHz 0.34mm<sup>2</sup> Router for Network-on-Chip Applications 2007 ·Sriram Vangal,(unknown),Jason Howard,Saurabh Dighe,Nitin Borkar,Atila Alvandpour	25
14	A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization 2006 ·IEEE Journal of Solid-State Circuits ·Sriram Vangal,Yatin Hoskote,Nitin Borkar,Atila Alvandpour	49
15	A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS 2003 ·Sriram Vangal,Yatin Hoskote,Dinesh Somasekhar,Vasantha Erraguntla,Jason Howard,Greg Ruhl,(unknown),D. Finan,Sanu Mathew,Nitin Borkar	15
16	Selective node engineering for chip-level soft error rate improvement [in CMOS] 2003 ·Tanay Karnik,Sriram Vangal,(unknown),P. Hazucha,Vasantha Erraguntla,Shekhar Borkar	46
17	A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS 2003 ·IEEE Journal of Solid-State Circuits ·Yatin Hoskote,B. Bloechel,G. Dermer,Vasantha Erraguntla,D. Finan,Jason Howard,(unknown),S. Narendra,Greg Ruhl,James Tschanz,Sriram Vangal,(unknown),H. Wilson,Jianzhong Xu,Nitin Borkar	30
18	A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS 2003 ·Yatin Hoskote,Vasantha Erraguntla,D. Finan,Jason Howard,(unknown),S. Narendra,Greg Ruhl,James Tschanz,Sriram Vangal,(unknown),H. Wilson,Jianping Xu,Nitin Borkar	10
19	1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS 2003 ·2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·S. Narendra,(unknown),(unknown),Vasantha Erraguntla,H. Wilson,Sriram Vangal,(unknown),Erik Seligman,Rajesh V. Nair,A. Keshavarzi,B. Bloechel,G. Dermer,Randy Mooney,Nitin Borkar,Shekhar Borkar,Viviana De	44
20	A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes 2002 ·R. Nair,Nitin Borkar,(unknown),G. Dermer,(unknown),(unknown),(unknown),(unknown),(unknown),Erik Seligman,Sriram Vangal,(unknown)	14

About Sriram Vangal

Sriram Vangal is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 29 papers that have together received 2.0k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (19 papers), Interconnection Networks and Systems (12 papers) and Advancements in Semiconductor Devices and Circuit Design (8 papers). The work is most often cited by research in Hardware and Architecture (1.2k citations), Computer Networks and Communications (1.3k citations) and Electrical and Electronic Engineering (1.4k citations). Sriram Vangal has collaborated with scholars based in United States, Sweden and India. Frequent co-authors include Nitin Borkar, Yatin Hoskote, Shekhar Borkar, James Tschanz, Vasantha Erraguntla, Saurabh Dighe, Jason Howard, D. Finan, Vivek De and Tiju Jacob. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Micro.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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