Tanay Karnik

8.2k total citations · 2 hit papers
125 papers, 6.1k citations indexed

About

Tanay Karnik is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Tanay Karnik has authored 125 papers receiving a total of 6.1k indexed citations (citations by other indexed papers that have themselves been cited), including 116 papers in Electrical and Electronic Engineering, 36 papers in Hardware and Architecture and 16 papers in Biomedical Engineering. Recurrent topics in Tanay Karnik's work include Low-power high-performance VLSI design (54 papers), Semiconductor materials and devices (50 papers) and Advancements in Semiconductor Devices and Circuit Design (25 papers). Tanay Karnik is often cited by papers focused on Low-power high-performance VLSI design (54 papers), Semiconductor materials and devices (50 papers) and Advancements in Semiconductor Devices and Circuit Design (25 papers). Tanay Karnik collaborates with scholars based in United States, United Kingdom and India. Tanay Karnik's co-authors include Vivek De, Shekhar Borkar, P. Hazucha, S. Narendra, A. Keshavarzi, Jim Tschanz, James Tschanz, B. Bloechel, G. Schrom and Keith Bowman and has published in prestigious journals such as Journal of Applied Physics, IEEE Journal of Solid-State Circuits and IEEE Transactions on Magnetics.

In The Last Decade

Tanay Karnik

118 papers receiving 5.9k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Parameter variations and impact on circuits and microarchitecture

2003 1.1k citations Shekhar Borkar, Tanay Karnik et al. profile →
Characterization of soft errors caused by single event upsets in CMOS processes

2004 378 citations Tanay Karnik, P. Hazucha profile →

Peers

Countries citing papers authored by Tanay Karnik

Since Specialization

Citations

This map shows the geographic impact of Tanay Karnik's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tanay Karnik with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tanay Karnik more than expected).

Fields of papers citing papers by Tanay Karnik

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tanay Karnik. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tanay Karnik. The network helps show where Tanay Karnik may publish in the future.

Co-authorship network of co-authors of Tanay Karnik

This figure shows the co-authorship network connecting the top 25 collaborators of Tanay Karnik. A scholar is included among the top collaborators of Tanay Karnik based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tanay Karnik. Tanay Karnik is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology 2025 ·IEEE Solid-State Circuits Letters ·(unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Tanay Karnik	0
2	1.536TB/s/mm² Bandwidth Scalable Attention Accelerator with 22.5GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3 2025 ·(unknown), Srivatsa Srinivasa, (unknown), (unknown), (unknown), Paolo Aseron, Trang Thi Thu Nguyen, (unknown), Tanay Karnik	0
3	A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System 2025 ·Srivatsa Srinivasa, (unknown), (unknown), (unknown), Paolo Aseron, (unknown), Ravishankar Iyer, (unknown), (unknown), (unknown), Tanay Karnik	0
4	A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems 2024 ·(unknown), (unknown), (unknown), Satish Yada, (unknown), (unknown), (unknown), (unknown), Paolo Aseron, Trang Nguyen, (unknown), (unknown), (unknown), Yan Song, Tanay Karnik, (unknown), Vivek De	2
5	CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder 2023 ·(unknown), (unknown), (unknown), Tanay Karnik	1
6	F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors 2021 ·Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) ·(unknown), (unknown), Luca Benini, Tanay Karnik, Hsie-Chia Chang	2
7	Self-Powered IOT System for Edge Inference 2020 ·(unknown), Tanay Karnik, (unknown), (unknown), Suhwan Kim, (unknown), Ankit Gupta, Krishnan Ravichandran, (unknown), Angela Nicoarǎ	0
8	Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface 2019 ·Srinivasan Gopal, Deukhyoun Heo, Tanay Karnik	1
9	Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems 2018 ·Lavanya Subramanian, Kaushik Vaidyanathan, (unknown), (unknown), Tanay Karnik, Hong Wang	3
10	Novel TFET circuits for high-performance energy-efficient heterogeneous MOSFET/TFET logic 2017 ·Daniel H. Morris, Uygar E. Avci, Kaushik Vaidyanathan, Huichu Liu, Tanay Karnik, Ian A. Young	3
11	Systemic optimization of on-chip thermoelectric cooling 2015 ·(unknown), Tanay Karnik, Rahul Khanna, Kelly Lofgreen, (unknown), (unknown), Kaushik Vaidyanathan	3
12	Design for test and reliability in ultimate CMOS 2012 ·M. Nicolaidis, Lorena Anghel, (unknown), Y. Zorian, Tanay Karnik, Keith Bowman, Jim Tschanz, Shih‐Lien Lu, (unknown), Arijit Raychowdhury, Muhammad Khellah, Jaydeep P. Kulkarni, Vivek De, D.R. Avresky	5
13	SRAM dynamic stability estimation using MPFP and its applications 2009 ·Microelectronics Journal ·Diaa Khalil, Muhammad Khellah, (unknown), Yehea Ismail, Tanay Karnik, Vivek De	9
14	Analytical Model for the Propagation Delay of Through Silicon Vias 2008 ·Diaa Khalil, Yehea Ismail, Muhammad Khellah, Tanay Karnik, Vivek De	36
15	A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction 2008 ·IEEE Journal of Solid-State Circuits ·Jianping Xu, P. Hazucha, (unknown), Paolo Aseron, (unknown), Fabrice Paillet, G. Schrom, James Tschanz, Vivek De, Tanay Karnik, G. Taylor	2
16	Integrated On-Chip Inductors with Magnetic Films 2006 ·Donald S. Gardner, G. Schrom, P. Hazucha, Fabrice Paillet, Tanay Karnik, Shekhar Borkar, (unknown), (unknown), (unknown)	34
17	High-Frequency DC-DC Conversion: Fact or Fiction 2006 ·Tanay Karnik, P. Hazucha, G. Schrom, Fabrice Paillet, Donald S. Gardner	14
18	Optimal Design of Monolithic Integrated DC-DC Converters 2006 ·G. Schrom, P. Hazucha, Fabrice Paillet, Donald S. Gardner, (unknown), Tanay Karnik	42
19	High-level hot carrier reliability-driven synthesis using macro-models 2002 ·Tanay Karnik, Chin-Chi Teng, Sung‐Mo Kang	1
20	An empirical model for accurate estimation of routing delay in FPGAs 1995 ·International Conference on Computer Aided Design ·Tanay Karnik, Sung‐Mo Kang	15

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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