Vivek De

18.3k total citations · 3 hit papers
368 papers, 12.8k citations indexed

About

Vivek De is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Vivek De has authored 368 papers receiving a total of 12.8k indexed citations (citations by other indexed papers that have themselves been cited), including 327 papers in Electrical and Electronic Engineering, 119 papers in Hardware and Architecture and 52 papers in Biomedical Engineering. Recurrent topics in Vivek De's work include Low-power high-performance VLSI design (197 papers), Advancements in Semiconductor Devices and Circuit Design (149 papers) and Semiconductor materials and devices (140 papers). Vivek De is often cited by papers focused on Low-power high-performance VLSI design (197 papers), Advancements in Semiconductor Devices and Circuit Design (149 papers) and Semiconductor materials and devices (140 papers). Vivek De collaborates with scholars based in United States, United Kingdom and Canada. Vivek De's co-authors include Shekhar Borkar, S. Narendra, Tanay Karnik, James Tschanz, A. Keshavarzi, J.D. Meindl, Jim Tschanz, D.A. Antoniadis, Anantha P. Chandrakasan and Keith Bowman and has published in prestigious journals such as Nature Communications, IEEE Transactions on Power Electronics and IEEE Journal of Solid-State Circuits.

In The Last Decade

Vivek De

354 papers receiving 12.2k citations

Hit Papers

Parameter variations and impact on circuits and microarch... 2002 2026 2010 2018 2003 2002 2010 250 500 750 1000
What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

  1. Parameter variations and impact on circuits and microarchitecture
    2003 1.1k citations Vivek De et al. profile →
  2. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    2002 548 citations James Tschanz, Vivek De et al. IEEE Journal of Solid-State Circuits profile →
  3. A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
    2010 303 citations Vivek De et al. IEEE Journal of Solid-State Circuits profile →

Peers

Vivek De
Comparison fields: 5 of 81
  • Electrical and Electronic Engineering 11.7k
  • Hardware and Architecture 4.9k
  • Biomedical Engineering 1.7k
  • Computer Networks and Communications 1.5k
  • Artificial Intelligence 621
Replace Shekhar Borkar with:
Shekhar Borkar United States
Sachin S. Sapatnekar United States
Mircea R. Stan United States
Subhasish Mitra United States
Borivoje Nikolić United States
Vijaykrishnan Narayanan United States
Bashir M. Al‐Hashimi United Kingdom
Mehdi B. Tahoori Germany
Martin D. F. Wong United States
Sung Kyu Lim United States
Shekhar Borkar United States View profile →
Citations per field, relative to Vivek De
Vivek De · 1×
Citations per year, relative to Vivek De
Vivek De · 1×

Countries citing papers authored by Vivek De

Since Specialization
Citations

This map shows the geographic impact of Vivek De's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Vivek De with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Vivek De more than expected).

Fields of papers citing papers by Vivek De

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Vivek De. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Vivek De. The network helps show where Vivek De may publish in the future.

Co-authorship network of co-authors of Vivek De

This figure shows the co-authorship network connecting the top 25 collaborators of Vivek De. A scholar is included among the top collaborators of Vivek De based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Vivek De. Vivek De is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
# Work Indexed citations
1
A Monolithic 5.7 A/mm2 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs
2025 ·IEEE Journal of Solid-State Circuits ·Xiaosen Liu, (unknown), (unknown), Nicolas Butzen, Sheldon Weng, Harish K. Krishnamurthy, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, (unknown), (unknown), James Tschanz, Vivek De
1
2
A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class
2024 ·IEEE Journal of Solid-State Circuits ·Suhwan Kim, Harish K. Krishnamurthy, (unknown), Nachiket Desai, Sheldon Weng, (unknown), Trương Thu Hương, (unknown), (unknown), Xiaosen Liu, Kaladhar Radhakrishnan, Krishnan Ravichandran, James Tschanz, Vivek De
1
3
A Fully-Digital Variation-Tolerant Runtime Detector for PCB-Level Probing Attack in a 28-nm CMOS
2023 ·IEEE Solid-State Circuits Letters ·(unknown), (unknown), Weifeng He, Sanu Mathew, Vivek De, Mingoo Seok
3
4
Mini-LEGO CPU Voltage Regulator
2023 ·IEEE Transactions on Power Electronics ·Youssef Elasser, Jae-Il Baek, Kaladhar Radhakrishnan, Houle Gan, (unknown), Harish K. Krishnamurthy, Xin Li, Shuai Jiang, Vivek De, Charles R. Sullivan, Minjie Chen
17
5
A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework
2023 ·IEEE Solid-State Circuits Letters ·Xiaosen Liu, Soner Yaldiz, (unknown), Steven M. Burns, Harish K. Krishnamurthy, Krishnan Ravichandran, (unknown), Nachiket Desai, Nicolas Butzen, James Tschanz, Vivek De
2
6
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors
2022 ·IEEE Journal of Solid-State Circuits ·Nachiket Desai, Han Wui Then, (unknown), Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James Tschanz, Vivek De
13
7
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning
2021 ·IEEE Journal of Solid-State Circuits ·Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, (unknown), Christopher Schaef, Krishnan Ravichandran, James Tschanz, Vivek De
13
8
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses
2021 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Saurabh Kumar, Minki Cho, Luke Everson, (unknown), (unknown), Carlos Tokunaga, Muhammad Khellah, James Tschanz, Vivek De, Chris H. Kim
1
9
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
2021 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Xiaosen Liu, Vikram Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew
18
10
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities
2021 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish K. Krishnamurthy, James Tschanz, Vivek De, Chris H. Kim
8
11
A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency
2020 ·IEEE Solid-State Circuits Letters ·Xiaosen Liu, Harish K. Krishnamurthy, (unknown), Jing Han, (unknown), (unknown), (unknown), Nachiket Desai, Krishnan Ravichandran, James Tschanz, Vivek De
4
12
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop
2020 ·IEEE Journal of Solid-State Circuits ·Suyoung Bang, Minki Cho, Pascal Meinerzhagen, (unknown), Muhammad Khellah, James Tschanz, Vivek De
6
13
Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array
2019 ·IEEE Transactions on Nuclear Science ·Saurabh Kumar, Minki Cho, Luke Everson, (unknown), Pascal Meinerzhagen, (unknown), (unknown), Carlos Tokunaga, Muhammad Khellah, James Tschanz, Vivek De, Chris H. Kim
11
14
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors
2019 ·IEEE Journal of Solid-State Circuits ·Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James Tschanz, Vivek De, Nachiket Desai, Harish K. Krishnamurthy, Xiaosen Liu, (unknown), Suhwan Kim, Sheldon Weng, (unknown), William J. Lambert
23
15
An All-Digital, $V$ MAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop
2019 ·IEEE Solid-State Circuits Letters ·Suyoung Bang, Minki Cho, Pascal Meinerzhagen, (unknown), Muhammad Khellah, James Tschanz, Vivek De
0
16
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications
2017 ·IEEE Journal of Solid-State Circuits ·Somnath Paul, (unknown), Ryan Kim, (unknown), Paolo Aseron, (unknown), Robert Sankman, Debendra Mallik, Tao Wang, Sriram Vangal, James Tschanz, Vivek De
46
17
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS
2017 ·IEEE Journal of Solid-State Circuits ·Harish K. Krishnamurthy, Vaibhav Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, (unknown), Nachiket Desai, Xiaosen Liu, Krishnan Ravichandran, James Tschanz, Vivek De
56
18
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
2016 ·IEEE Journal of Solid-State Circuits ·Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James Tschanz, Muhammad Khellah, Vivek De
35
19
Compiler Support for Reducing Leakage Energy Consumption
2003 ·Design, Automation, and Test in Europe ·Wei Zhang, Mahmut Kandemir, N. Vijaykrishnan, M.J. Irwin, Vivek De
25
20
Impact of Random Dopant Placement on CMOS Delay and Power Dissipation
1999 ·European Solid-State Device Research Conference ·Xizi Tang, Keith Bowman, J.C. Eble, Vivek De, J.D. Meindl
6

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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