Vasantha Erraguntla

2.7k total citations · 2 hit papers
20 papers, 1.3k citations indexed

About

Vasantha Erraguntla is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Vasantha Erraguntla has authored 20 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Electrical and Electronic Engineering, 12 papers in Hardware and Architecture and 9 papers in Computer Networks and Communications. Recurrent topics in Vasantha Erraguntla's work include Low-power high-performance VLSI design (10 papers), Interconnection Networks and Systems (8 papers) and Parallel Computing and Optimization Techniques (6 papers). Vasantha Erraguntla is often cited by papers focused on Low-power high-performance VLSI design (10 papers), Interconnection Networks and Systems (8 papers) and Parallel Computing and Optimization Techniques (6 papers). Vasantha Erraguntla collaborates with scholars based in United States, India and Israel. Vasantha Erraguntla's co-authors include Nitin Borkar, Shekhar Borkar, Jason Howard, Greg Ruhl, Saurabh Dighe, Shailendra Jain, Sriram Vangal, Tiju Jacob, Yatin Hoskote and James Tschanz and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

In The Last Decade

Vasantha Erraguntla

20 papers receiving 1.3k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

2008 466 citations Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits profile →
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

2010 303 citations Jason Howard, Saurabh Dighe et al. IEEE Journal of Solid-State Circuits profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Vasantha Erraguntla United States	14	838	834	831	99	81	20	1.3k
Jason Howard United States	13	1.3k 1.5×	1.2k 1.4×	1.0k 1.2×	150 1.5×	58 0.7×	24	1.8k
Saurabh Dighe United States	10	1.2k 1.5×	1.2k 1.4×	1.0k 1.2×	150 1.5×	54 0.7×	13	1.7k
Victor Zyuban United States	22	1.1k 1.3×	1.6k 1.9×	1.5k 1.8×	78 0.8×	99 1.2×	49	2.3k
Karam S. Chatha United States	24	1.3k 1.6×	1.4k 1.6×	841 1.0×	136 1.4×	26 0.3×	75	1.7k
Greg Ruhl United States	11	876 1.0×	771 0.9×	670 0.8×	93 0.9×	33 0.4×	11	1.2k
Jens Sparsø Denmark	21	1.1k 1.3×	1.2k 1.4×	917 1.1×	119 1.2×	163 2.0×	95	1.7k
Siamak Mohammadi Iran	16	501 0.6×	351 0.4×	539 0.6×	75 0.8×	55 0.7×	112	891
Shaahin Hessabi Iran	17	481 0.6×	472 0.6×	599 0.7×	58 0.6×	24 0.3×	100	1.1k
Tiju Jacob United States	7	928 1.1×	799 1.0×	684 0.8×	129 1.3×	28 0.3×	8	1.2k
J. van Meerbergen Netherlands	18	1.0k 1.2×	1.0k 1.2×	514 0.6×	116 1.2×	58 0.7×	83	1.5k

Countries citing papers authored by Vasantha Erraguntla

Since Specialization

Citations

This map shows the geographic impact of Vasantha Erraguntla's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Vasantha Erraguntla with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Vasantha Erraguntla more than expected).

Fields of papers citing papers by Vasantha Erraguntla

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Vasantha Erraguntla. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Vasantha Erraguntla. The network helps show where Vasantha Erraguntla may publish in the future.

Co-authorship network of co-authors of Vasantha Erraguntla

This figure shows the co-authorship network connecting the top 25 collaborators of Vasantha Erraguntla. A scholar is included among the top collaborators of Vasantha Erraguntla based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Vasantha Erraguntla. Vasantha Erraguntla is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Dighe, Saurabh, Shailendra Jain, Satish Yada, et al.. (2012). An IA-32 processor with a wide voltage operating range in 32nm CMOS. 1–37. 1 indexed citations

Jain, Shailendra, Tiju Jacob, Vasantha Erraguntla, et al.. (2011). A 2 Tb/s 6<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. IEEE Journal of Solid-State Circuits. 46(4). 757–766. 77 indexed citations

Srinivasan, Suresh, Sanu Mathew, R. Ramanarayanan, et al.. (2010). 2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS. 203–204. 46 indexed citations

Ramanarayanan, R., Sanu Mathew, Farhana Sheikh, et al.. (2010). 18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. 210–213. 13 indexed citations

Dighe, Saurabh, Sriram Vangal, Paolo Aseron, et al.. (2010). Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE Journal of Solid-State Circuits. 46(1). 184–193. 95 indexed citations

Jain, Shailendra, et al.. (2010). A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. 252–257. 11 indexed citations

Howard, Jason, Saurabh Dighe, Sriram Vangal, et al.. (2010). A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE Journal of Solid-State Circuits. 46(1). 173–183. 303 indexed citations breakdown →

Dighe, Saurabh, Paolo Aseron, Tiju Jacob, et al.. (2010). Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. 174–175. 45 indexed citations

Jain, Shailendra, Tiju Jacob, Vasantha Erraguntla, et al.. (2010). A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS. 79–80. 18 indexed citations

10.

Srinivasan, Suresh, Sanu Mathew, Vasantha Erraguntla, & Ram Krishnamurthy. (2009). A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. 301–306. 33 indexed citations

11.

Ramanarayanan, R., Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, & Shay Gueron. (2008). A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. 273–278. 3 indexed citations

12.

Vangal, Sriram, Jason Howard, Greg Ruhl, et al.. (2008). An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 43(1). 29–41. 466 indexed citations breakdown →

13.

Borkar, Nitin, Erik Seligman, Vasantha Erraguntla, et al.. (2005). 5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 2. 334–535. 1 indexed citations

14.

Narendra, S., James Tschanz, B. Bloechel, et al.. (2004). Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique. 156–518. 64 indexed citations

15.

Vangal, Sriram, Yatin Hoskote, Dinesh Somasekhar, et al.. (2003). A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS. 1. 334–497. 15 indexed citations

16.

Karnik, Tanay, et al.. (2003). Selective node engineering for chip-level soft error rate improvement [in CMOS]. 204–205. 46 indexed citations

17.

Hoskote, Yatin, B. Bloechel, G. Dermer, et al.. (2003). A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS. IEEE Journal of Solid-State Circuits. 38(11). 1866–1875. 30 indexed citations

18.

Hoskote, Yatin, Vasantha Erraguntla, D. Finan, et al.. (2003). A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS. 1. 258–492. 10 indexed citations

19.

Narendra, S., Vasantha Erraguntla, H. Wilson, et al.. (2003). 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 270–466. 44 indexed citations

20.

Vangal, Sriram, Nitin Borkar, Erik Seligman, et al.. (2003). A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 412–478. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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