Amit Agarwal

3.7k total citations
102 papers, 2.7k citations indexed

About

Amit Agarwal is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, Amit Agarwal has authored 102 papers receiving a total of 2.7k indexed citations (citations by other indexed papers that have themselves been cited), including 69 papers in Electrical and Electronic Engineering, 41 papers in Hardware and Architecture and 24 papers in Artificial Intelligence. Recurrent topics in Amit Agarwal's work include Low-power high-performance VLSI design (41 papers), Semiconductor materials and devices (27 papers) and Advancements in Semiconductor Devices and Circuit Design (23 papers). Amit Agarwal is often cited by papers focused on Low-power high-performance VLSI design (41 papers), Semiconductor materials and devices (27 papers) and Advancements in Semiconductor Devices and Circuit Design (23 papers). Amit Agarwal collaborates with scholars based in United States, India and United Kingdom. Amit Agarwal's co-authors include Kaushik Roy, Ram Krishnamurthy, Mark Anders, Himanshu Kaul, Sanu Mathew, Steven Hsu, Sudhir Satpathy, Bipul C. Paul, Steven K. Hsu and Hai Li and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Amit Agarwal

100 papers receiving 2.6k citations

Peers

Countries citing papers authored by Amit Agarwal

Since Specialization

Citations

This map shows the geographic impact of Amit Agarwal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Amit Agarwal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Amit Agarwal more than expected).

Fields of papers citing papers by Amit Agarwal

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Amit Agarwal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Amit Agarwal. The network helps show where Amit Agarwal may publish in the future.

Co-authorship network of co-authors of Amit Agarwal

This figure shows the co-authorship network connecting the top 25 collaborators of Amit Agarwal. A scholar is included among the top collaborators of Amit Agarwal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Amit Agarwal. Amit Agarwal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	AccessEval: Benchmarking Disability Bias in Large Language Models 2025 ·Subhrakanta Panda, Amit Agarwal, (unknown)	1
2	Who's Asking? Investigating Bias Through the Lens of Disability-Framed Queries in LLMs 2025 ·(unknown), (unknown), (unknown), Amit Agarwal, (unknown)	0
3	Tokenization Matters: Improving Zero-Shot NER for Indic Languages 2025 ·(unknown), (unknown), Amit Agarwal	0
4	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS 2022 ·2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Raghavan Kumar, Vikram Suresh, Sachin Taneja, Mark Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew	2
5	Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities 2021 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish K. Krishnamurthy, James Tschanz, Vivek De, Chris H. Kim	8
6	A 4900-$\mu$ m² 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition 2020 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Vikram Suresh, Monodeep Kar, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew	17
7	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS 2019 ·Steven Hsu, Amit Agarwal, Monodeep Kar, Mark Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De	3
8	A 4900×m² 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition 2019 ·Raghavan Kumar, Vikram Suresh, Monodeep Kar, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew	2
9	Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS 2018 ·Himanshu Kaul, Mark Anders, Sanu Mathew, Vikram Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy	4
10	340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS 2015 ·IEEE Journal of Solid-State Circuits ·Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Krishnamurthy	106
11	16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS 2014 ·Sanu Mathew, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram Krishnamurthy, Vivek De	192
12	340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS 2014 ·Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, Mark Anders, (unknown), Amit Agarwal, Steven Hsu, Ram Krishnamurthy	9
13	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS 2012 ·IEEE Journal of Solid-State Circuits ·Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar	16
14	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS 2010 ·IEEE Journal of Solid-State Circuits ·Himanshu Kaul, Mark Anders, Sanu Mathew, Steven K. Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar	32
15	Fault tolerant placement and defect reconfiguration for nano-FPGAs 2008 ·International Conference on Computer Aided Design ·Amit Agarwal, Jason Cong, (unknown)	6
16	Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations 2005 ·International Conference on Computer Aided Design ·Amit Agarwal, Kunhyuk Kang, Kaushik Roy	20
17	Accurate estimation and modeling of total chip leakage considering inter- & amp; intra-die process variations 2005 ·Amit Agarwal, Kunhyuk Kang, Kaushik Roy	18
18	A novel fault tolerant cache to improve yield in nanometer technologies 2004 ·Amit Agarwal, Bipul C. Paul, Kaushik Roy	12
19	Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology 2003 ·Design, Automation, and Test in Europe ·Amit Agarwal, Kaushik Roy, T. N. Vijaykumar	20
20	Reducing set-associative cache energy via way-prediction and selective direct-mapping 2001 ·International Symposium on Microarchitecture ·Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy	154

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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