Jason Howard

3.3k total citations · 3 hit papers
24 papers, 1.8k citations indexed

About

Jason Howard is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Jason Howard has authored 24 papers receiving a total of 1.8k indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 14 papers in Computer Networks and Communications and 13 papers in Hardware and Architecture. Recurrent topics in Jason Howard's work include Interconnection Networks and Systems (12 papers), Parallel Computing and Optimization Techniques (9 papers) and Low-power high-performance VLSI design (9 papers). Jason Howard is often cited by papers focused on Interconnection Networks and Systems (12 papers), Parallel Computing and Optimization Techniques (9 papers) and Low-power high-performance VLSI design (9 papers). Jason Howard collaborates with scholars based in United States, India and Sweden. Jason Howard's co-authors include Nitin Borkar, Saurabh Dighe, Shailendra Jain, Greg Ruhl, James Tschanz, Tiju Jacob, Shekhar Borkar, D. Finan, Yatin Hoskote and Vasantha Erraguntla and has published in prestigious journals such as IEEE Access, IEEE Journal of Solid-State Circuits and IEEE Micro.

In The Last Decade

Jason Howard

22 papers receiving 1.7k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

2007 474 citations Sriram Vangal, Jason Howard et al. profile →
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

2008 466 citations Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits profile →
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

2010 303 citations Jason Howard, Saurabh Dighe et al. IEEE Journal of Solid-State Circuits profile →

Peers

Countries citing papers authored by Jason Howard

Since Specialization

Citations

This map shows the geographic impact of Jason Howard's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jason Howard with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jason Howard more than expected).

Fields of papers citing papers by Jason Howard

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jason Howard. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jason Howard. The network helps show where Jason Howard may publish in the future.

Co-authorship network of co-authors of Jason Howard

This figure shows the co-authorship network connecting the top 25 collaborators of Jason Howard. A scholar is included among the top collaborators of Jason Howard based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jason Howard. Jason Howard is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation 2025 ·IEEE Access ·(unknown), Martin Reisslein, Akhilesh S. Thyagaturu, (unknown), (unknown), Jason Howard, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown)	0
2	BiFrost: A Composable, Resilient Interconnect Network Architecture for Scalable Artificial Intelligence Systems 2025 ·IEEE Micro ·(unknown), Hong Wang, Jason Howard, (unknown), Fabrizio Petrini, (unknown), (unknown), Anil V. Rao, (unknown)	0
3	The First Direct Mesh-to-Mesh Photonic Fabric 2024 ·IEEE Micro ·Jason Howard, (unknown), (unknown)	1
4	The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor 2023 ·IEEE Micro ·(unknown), (unknown), Vincent Cavé, Fabio Checconi, (unknown), Stijn Eyerman, (unknown), Wim Heirman, Jason Howard, Ibrahim Hur, (unknown), (unknown), Kevin Ma, (unknown), Robert Pawłowski, Fabrizio Petrini, (unknown), (unknown), Jesmin Jahan Tithi, (unknown)	4
5	Resiliency for many-core system on a chip 2014 ·Tanay Karnik, James Tschanz, Nitin Borkar, Jason Howard, Sriram Vangal, Vivek De, Shekhar Borkar	2
6	An IA-32 processor with a wide voltage operating range in 32nm CMOS 2012 ·(unknown), Saurabh Dighe, Shailendra Jain, (unknown), Satish Yada, (unknown), (unknown), (unknown), Sriram Muthukumar, (unknown), Arun Kumar, (unknown), R. Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram Vangal, Paolo Aseron, (unknown), Nitin Borkar	1
7	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor 2010 ·IEEE Journal of Solid-State Circuits ·Saurabh Dighe, Sriram Vangal, Paolo Aseron, Sachin Sharma Ashok Kumar, Tiju Jacob, Keith Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar	95
8	A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS 2010 ·Jason Howard	9
9	2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology 2009 ·IEEE Journal of Solid-State Circuits ·Dinesh Somasekhar, Yibin Ye, Paolo Aseron, Shih‐Lien Lu, Muhammad Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Borkar, Vivek De, A. Keshavarzi	69
10	An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS breakdown → 2008 ·IEEE Journal of Solid-State Circuits ·Sriram Vangal, Jason Howard, Greg Ruhl, Saurabh Dighe, H. Wilson, James Tschanz, D. Finan, (unknown), Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Hoskote, Nitin Borkar, Shekhar Borkar	466
11	2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process 2008 ·Dinesh Somasekhar, Yibin Ye, Paolo Aseron, Shih‐Lien Lu, Muhammad Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Borkar, Vivek De, A. Keshavarzi	20
12	An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS breakdown → 2007 ·Sriram Vangal, Jason Howard, (unknown), Saurabh Dighe, (unknown), James Tschanz, D. Finan, Prakash Iyer, (unknown), Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar	474
13	A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor 2007 ·IEEE Journal of Solid-State Circuits ·Muhammad Khellah, Dinesh Somasekhar, (unknown), Nam Sung Kim, Jason Howard, Greg Ruhl, (unknown), James Tschanz, Nitin Borkar, Fatih Hamzaoglu, (unknown), (unknown), Guomin Zhang, Vivek De	45
14	A 5.1GHz 0.34mm<sup>2</sup> Router for Network-on-Chip Applications 2007 ·Sriram Vangal, (unknown), Jason Howard, Saurabh Dighe, Nitin Borkar, Atila Alvandpour	25
15	A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS 2006 ·Muhammad Khellah, Nam Sung Kim, Jason Howard, Greg Ruhl, (unknown), (unknown), (unknown), Dinesh Somasekhar, Nitin Borkar, (unknown), (unknown), (unknown), Kedong Zhang, Vivek De	23
16	Testing high-speed IO links using on-die circuitry 2006 ·Prakash Iyer, (unknown), Bryan Casper, Jason Howard	10
17	A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS 2003 ·Sriram Vangal, Yatin Hoskote, Dinesh Somasekhar, Vasantha Erraguntla, Jason Howard, Greg Ruhl, (unknown), D. Finan, Sanu Mathew, Nitin Borkar	15
18	A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS 2003 ·IEEE Journal of Solid-State Circuits ·Yatin Hoskote, B. Bloechel, G. Dermer, Vasantha Erraguntla, D. Finan, Jason Howard, (unknown), S. Narendra, Greg Ruhl, James Tschanz, Sriram Vangal, (unknown), H. Wilson, Jianzhong Xu, Nitin Borkar	30
19	A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS 2003 ·Yatin Hoskote, Vasantha Erraguntla, D. Finan, Jason Howard, (unknown), S. Narendra, Greg Ruhl, James Tschanz, Sriram Vangal, (unknown), H. Wilson, Jianping Xu, Nitin Borkar	10
20	The execution unit for the VLSI 432 general data processor 1981 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), Anna L. Goodman, Jason Howard, (unknown)	6

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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